\doxysection{stm32h7xx\+\_\+hal\+\_\+rcc.\+h}
\hypertarget{stm32h7xx__hal__rcc_8h_source}{}\label{stm32h7xx__hal__rcc_8h_source}\index{C:/Users/ASUS/Desktop/dm-\/ctrlH7-\/balance-\/9025test/Drivers/STM32H7xx\_HAL\_Driver/Inc/stm32h7xx\_hal\_rcc.h@{C:/Users/ASUS/Desktop/dm-\/ctrlH7-\/balance-\/9025test/Drivers/STM32H7xx\_HAL\_Driver/Inc/stm32h7xx\_hal\_rcc.h}}
\mbox{\hyperlink{stm32h7xx__hal__rcc_8h}{Go to the documentation of this file.}}
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\DoxyCodeLine{00018\ \textcolor{comment}{/*\ Define\ to\ prevent\ recursive\ inclusion\ -\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/*/}}
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\DoxyCodeLine{00026\ \textcolor{comment}{/*\ Includes\ -\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/*/}}
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\DoxyCodeLine{00037\ \textcolor{comment}{/*\ Exported\ types\ -\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/*/}}
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\DoxyCodeLine{00047\ \{}
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\DoxyCodeLine{00117\ \}\ \mbox{\hyperlink{struct_r_c_c___osc_init_type_def}{RCC\_OscInitTypeDef}};}
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\DoxyCodeLine{00122\ \textcolor{keyword}{typedef}\ \textcolor{keyword}{struct}}
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\DoxyCodeLine{00145\ \}\ \mbox{\hyperlink{struct_r_c_c___clk_init_type_def}{RCC\_ClkInitTypeDef}};}
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\DoxyCodeLine{00151\ \textcolor{comment}{/*\ Exported\ constants\ -\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/*/}}
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\DoxyCodeLine{00551\ \textcolor{preprocessor}{\#define\ RCC\_RTCCLKSOURCE\_HSE\_DIV63\ \ \ \ \ \ \ (0x0003F300U)}}
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\DoxyCodeLine{00558\ }
\DoxyCodeLine{00562\ \textcolor{preprocessor}{\#define\ RCC\_MCO1\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x00000000U)}}
\DoxyCodeLine{00563\ \textcolor{preprocessor}{\#define\ RCC\_MCO2\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x00000001U)}}
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\DoxyCodeLine{00572\ \textcolor{preprocessor}{\#define\ RCC\_MCO1SOURCE\_HSI\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x00000000U)}}
\DoxyCodeLine{00573\ \textcolor{preprocessor}{\#define\ RCC\_MCO1SOURCE\_LSE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ RCC\_CFGR\_MCO1\_0}}
\DoxyCodeLine{00574\ \textcolor{preprocessor}{\#define\ RCC\_MCO1SOURCE\_HSE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ RCC\_CFGR\_MCO1\_1}}
\DoxyCodeLine{00575\ \textcolor{preprocessor}{\#define\ RCC\_MCO1SOURCE\_PLL1QCLK\ \ \ \ \ \ \ \ \ \ ((uint32\_t)RCC\_CFGR\_MCO1\_0\ |\ RCC\_CFGR\_MCO1\_1)}}
\DoxyCodeLine{00576\ \textcolor{preprocessor}{\#define\ RCC\_MCO1SOURCE\_HSI48\ \ \ \ \ \ \ \ \ \ \ \ \ \ RCC\_CFGR\_MCO1\_2}}
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\DoxyCodeLine{00585\ \textcolor{preprocessor}{\#define\ RCC\_MCO2SOURCE\_SYSCLK\ \ \ \ \ \ \ \ \ \ \ \ (0x00000000U)}}
\DoxyCodeLine{00586\ \textcolor{preprocessor}{\#define\ RCC\_MCO2SOURCE\_PLL2PCLK\ \ \ \ \ \ \ \ \ \ RCC\_CFGR\_MCO2\_0}}
\DoxyCodeLine{00587\ \textcolor{preprocessor}{\#define\ RCC\_MCO2SOURCE\_HSE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ RCC\_CFGR\_MCO2\_1}}
\DoxyCodeLine{00588\ \textcolor{preprocessor}{\#define\ RCC\_MCO2SOURCE\_PLLCLK\ \ \ \ \ \ \ \ \ \ \ \ ((uint32\_t)RCC\_CFGR\_MCO2\_0\ |\ RCC\_CFGR\_MCO2\_1)}}
\DoxyCodeLine{00589\ \textcolor{preprocessor}{\#define\ RCC\_MCO2SOURCE\_CSICLK\ \ \ \ \ \ \ \ \ \ \ \ RCC\_CFGR\_MCO2\_2}}
\DoxyCodeLine{00590\ \textcolor{preprocessor}{\#define\ RCC\_MCO2SOURCE\_LSICLK\ \ \ \ \ \ \ \ \ \ \ \ ((uint32\_t)RCC\_CFGR\_MCO2\_0\ |\ RCC\_CFGR\_MCO2\_2)}}
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\DoxyCodeLine{00599\ \textcolor{preprocessor}{\#define\ RCC\_MCODIV\_1\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ RCC\_CFGR\_MCO1PRE\_0}}
\DoxyCodeLine{00600\ \textcolor{preprocessor}{\#define\ RCC\_MCODIV\_2\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ RCC\_CFGR\_MCO1PRE\_1}}
\DoxyCodeLine{00601\ \textcolor{preprocessor}{\#define\ RCC\_MCODIV\_3\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((uint32\_t)RCC\_CFGR\_MCO1PRE\_0\ |\ RCC\_CFGR\_MCO1PRE\_1)}}
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\DoxyCodeLine{00603\ \textcolor{preprocessor}{\#define\ RCC\_MCODIV\_5\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((uint32\_t)RCC\_CFGR\_MCO1PRE\_0\ |\ RCC\_CFGR\_MCO1PRE\_2)}}
\DoxyCodeLine{00604\ \textcolor{preprocessor}{\#define\ RCC\_MCODIV\_6\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((uint32\_t)RCC\_CFGR\_MCO1PRE\_1\ |\ RCC\_CFGR\_MCO1PRE\_2)}}
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\DoxyCodeLine{00607\ \textcolor{preprocessor}{\#define\ RCC\_MCODIV\_9\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((uint32\_t)RCC\_CFGR\_MCO1PRE\_0\ |\ RCC\_CFGR\_MCO1PRE\_3)}}
\DoxyCodeLine{00608\ \textcolor{preprocessor}{\#define\ RCC\_MCODIV\_10\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((uint32\_t)RCC\_CFGR\_MCO1PRE\_1\ |\ RCC\_CFGR\_MCO1PRE\_3)}}
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\DoxyCodeLine{00610\ \textcolor{preprocessor}{\#define\ RCC\_MCODIV\_12\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((uint32\_t)RCC\_CFGR\_MCO1PRE\_2\ |\ RCC\_CFGR\_MCO1PRE\_3)}}
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\DoxyCodeLine{00619\ }
\DoxyCodeLine{00623\ \textcolor{preprocessor}{\#define\ RCC\_IT\_LSIRDY\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x00000001U)}}
\DoxyCodeLine{00624\ \textcolor{preprocessor}{\#define\ RCC\_IT\_LSERDY\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x00000002U)}}
\DoxyCodeLine{00625\ \textcolor{preprocessor}{\#define\ RCC\_IT\_HSIRDY\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x00000004U)}}
\DoxyCodeLine{00626\ \textcolor{preprocessor}{\#define\ RCC\_IT\_HSERDY\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x00000008U)}}
\DoxyCodeLine{00627\ \textcolor{preprocessor}{\#define\ RCC\_IT\_CSIRDY\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x00000010U)}}
\DoxyCodeLine{00628\ \textcolor{preprocessor}{\#define\ RCC\_IT\_HSI48RDY\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x00000020U)}}
\DoxyCodeLine{00629\ \textcolor{preprocessor}{\#define\ RCC\_IT\_PLLRDY\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x00000040U)}}
\DoxyCodeLine{00630\ \textcolor{preprocessor}{\#define\ RCC\_IT\_PLL2RDY\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x00000080U)}}
\DoxyCodeLine{00631\ \textcolor{preprocessor}{\#define\ RCC\_IT\_PLL3RDY\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x00000100U)}}
\DoxyCodeLine{00632\ \textcolor{preprocessor}{\#define\ RCC\_IT\_LSECSS\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x00000200U)}}
\DoxyCodeLine{00633\ \textcolor{preprocessor}{\#define\ RCC\_IT\_CSS\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x00000400U)}\textcolor{preprocessor}{}}
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\DoxyCodeLine{00648\ \textcolor{comment}{/*\ Flags\ in\ the\ CR\ register\ */}}
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\DoxyCodeLine{01494\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ while(0)}}
\DoxyCodeLine{01495\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ GPIOI\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{01496\ }
\DoxyCodeLine{01497\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_GPIOJ\_CLK\_ENABLE()\ \ \ do\ \{\ \(\backslash\)}}
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\DoxyCodeLine{01499\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC-\/>AHB4ENR,\ RCC\_AHB4ENR\_GPIOJEN);\(\backslash\)}}
\DoxyCodeLine{01500\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ an\ RCC\ peripheral\ clock\ enabling\ */}\textcolor{preprocessor}{\ \(\backslash\)}}
\DoxyCodeLine{01501\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC-\/>AHB4ENR,\ RCC\_AHB4ENR\_GPIOJEN);\(\backslash\)}}
\DoxyCodeLine{01502\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ UNUSED(tmpreg);\ \(\backslash\)}}
\DoxyCodeLine{01503\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ while(0)}}
\DoxyCodeLine{01504\ }
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\DoxyCodeLine{01506\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_IO\ uint32\_t\ tmpreg;\ \(\backslash\)}}
\DoxyCodeLine{01507\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC-\/>AHB4ENR,\ RCC\_AHB4ENR\_GPIOKEN);\(\backslash\)}}
\DoxyCodeLine{01508\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ an\ RCC\ peripheral\ clock\ enabling\ */}\textcolor{preprocessor}{\ \(\backslash\)}}
\DoxyCodeLine{01509\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC-\/>AHB4ENR,\ RCC\_AHB4ENR\_GPIOKEN);\(\backslash\)}}
\DoxyCodeLine{01510\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ UNUSED(tmpreg);\ \(\backslash\)}}
\DoxyCodeLine{01511\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ while(0)}}
\DoxyCodeLine{01512\ }
\DoxyCodeLine{01513\ \textcolor{preprocessor}{\#if\ defined(RCC\_AHB4ENR\_CRCEN)}}
\DoxyCodeLine{01514\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_CRC\_CLK\_ENABLE()\ \ \ do\ \{\ \(\backslash\)}}
\DoxyCodeLine{01515\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_IO\ uint32\_t\ tmpreg;\ \(\backslash\)}}
\DoxyCodeLine{01516\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC-\/>AHB4ENR,\ RCC\_AHB4ENR\_CRCEN);\(\backslash\)}}
\DoxyCodeLine{01517\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ an\ RCC\ peripheral\ clock\ enabling\ */}\textcolor{preprocessor}{\ \(\backslash\)}}
\DoxyCodeLine{01518\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC-\/>AHB4ENR,\ RCC\_AHB4ENR\_CRCEN);\(\backslash\)}}
\DoxyCodeLine{01519\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ UNUSED(tmpreg);\ \(\backslash\)}}
\DoxyCodeLine{01520\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ while(0)}}
\DoxyCodeLine{01521\ \textcolor{preprocessor}{\#endif}}
\DoxyCodeLine{01522\ }
\DoxyCodeLine{01523\ \textcolor{preprocessor}{\#if\ defined(BDMA2)}}
\DoxyCodeLine{01524\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_BDMA2\_CLK\_ENABLE()\ \ \ do\ \{\ \(\backslash\)}}
\DoxyCodeLine{01525\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_IO\ uint32\_t\ tmpreg;\ \(\backslash\)}}
\DoxyCodeLine{01526\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC-\/>AHB4ENR,\ RCC\_AHB4ENR\_BDMA2EN);\(\backslash\)}}
\DoxyCodeLine{01527\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ an\ RCC\ peripheral\ clock\ enabling\ */}\textcolor{preprocessor}{\ \(\backslash\)}}
\DoxyCodeLine{01528\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC-\/>AHB4ENR,\ RCC\_AHB4ENR\_BDMA2EN);\(\backslash\)}}
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\DoxyCodeLine{01530\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ while(0)}}
\DoxyCodeLine{01531\ }
\DoxyCodeLine{01532\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_BDMA\_CLK\_ENABLE()\ \ \_\_HAL\_RCC\_BDMA2\_CLK\_ENABLE()\ \ }\textcolor{comment}{/*\ for\ API\ backward\ compatibility*/}\textcolor{preprocessor}{}}
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\DoxyCodeLine{01534\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_BDMA\_CLK\_ENABLE()\ \ \ do\ \{\ \(\backslash\)}}
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\DoxyCodeLine{01536\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC-\/>AHB4ENR,\ RCC\_AHB4ENR\_BDMAEN);\(\backslash\)}}
\DoxyCodeLine{01537\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ an\ RCC\ peripheral\ clock\ enabling\ */}\textcolor{preprocessor}{\ \(\backslash\)}}
\DoxyCodeLine{01538\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC-\/>AHB4ENR,\ RCC\_AHB4ENR\_BDMAEN);\(\backslash\)}}
\DoxyCodeLine{01539\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ UNUSED(tmpreg);\ \(\backslash\)}}
\DoxyCodeLine{01540\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ while(0)}}
\DoxyCodeLine{01541\ \textcolor{preprocessor}{\#endif}}
\DoxyCodeLine{01542\ }
\DoxyCodeLine{01543\ \textcolor{preprocessor}{\#if\ defined(ADC3)}}
\DoxyCodeLine{01544\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_ADC3\_CLK\_ENABLE()\ \ \ do\ \{\ \(\backslash\)}}
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\DoxyCodeLine{01547\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ an\ RCC\ peripheral\ clock\ enabling\ */}\textcolor{preprocessor}{\ \(\backslash\)}}
\DoxyCodeLine{01548\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC-\/>AHB4ENR,\ RCC\_AHB4ENR\_ADC3EN);\(\backslash\)}}
\DoxyCodeLine{01549\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ UNUSED(tmpreg);\ \(\backslash\)}}
\DoxyCodeLine{01550\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ while(0)}}
\DoxyCodeLine{01551\ \textcolor{preprocessor}{\#endif}}
\DoxyCodeLine{01552\ }
\DoxyCodeLine{01553\ \textcolor{preprocessor}{\#if\ defined(RCC\_AHB4ENR\_HSEMEN)}}
\DoxyCodeLine{01554\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_HSEM\_CLK\_ENABLE()\ \ \ do\ \{\ \(\backslash\)}}
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\DoxyCodeLine{01557\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ an\ RCC\ peripheral\ clock\ enabling\ */}\textcolor{preprocessor}{\ \(\backslash\)}}
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\DoxyCodeLine{01560\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ while(0)}}
\DoxyCodeLine{01561\ \textcolor{preprocessor}{\#endif}}
\DoxyCodeLine{01562\ }
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\DoxyCodeLine{01571\ \textcolor{preprocessor}{\#endif}}
\DoxyCodeLine{01572\ }
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\DoxyCodeLine{01577\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC-\/>AHB4ENR,\ RCC\_AHB4ENR\_BKPRAMEN);\(\backslash\)}}
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\DoxyCodeLine{01580\ }
\DoxyCodeLine{01581\ }
\DoxyCodeLine{01582\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_GPIOA\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC-\/>AHB4ENR)\ \&=\ \string~\ (RCC\_AHB4ENR\_GPIOAEN)}}
\DoxyCodeLine{01583\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_GPIOB\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC-\/>AHB4ENR)\ \&=\ \string~\ (RCC\_AHB4ENR\_GPIOBEN)}}
\DoxyCodeLine{01584\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_GPIOC\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC-\/>AHB4ENR)\ \&=\ \string~\ (RCC\_AHB4ENR\_GPIOCEN)}}
\DoxyCodeLine{01585\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_GPIOD\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC-\/>AHB4ENR)\ \&=\ \string~\ (RCC\_AHB4ENR\_GPIODEN)}}
\DoxyCodeLine{01586\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_GPIOE\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC-\/>AHB4ENR)\ \&=\ \string~\ (RCC\_AHB4ENR\_GPIOEEN)}}
\DoxyCodeLine{01587\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_GPIOF\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC-\/>AHB4ENR)\ \&=\ \string~\ (RCC\_AHB4ENR\_GPIOFEN)}}
\DoxyCodeLine{01588\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_GPIOG\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC-\/>AHB4ENR)\ \&=\ \string~\ (RCC\_AHB4ENR\_GPIOGEN)}}
\DoxyCodeLine{01589\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_GPIOH\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC-\/>AHB4ENR)\ \&=\ \string~\ (RCC\_AHB4ENR\_GPIOHEN)}}
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\DoxyCodeLine{01591\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_GPIOI\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC-\/>AHB4ENR)\ \&=\ \string~\ (RCC\_AHB4ENR\_GPIOIEN)}}
\DoxyCodeLine{01592\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ GPIOI\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{01593\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_GPIOJ\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC-\/>AHB4ENR)\ \&=\ \string~\ (RCC\_AHB4ENR\_GPIOJEN)}}
\DoxyCodeLine{01594\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_GPIOK\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC-\/>AHB4ENR)\ \&=\ \string~\ (RCC\_AHB4ENR\_GPIOKEN)}}
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\DoxyCodeLine{01596\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_CRC\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ \ \ (RCC-\/>AHB4ENR)\ \&=\ \string~\ (RCC\_AHB4ENR\_CRCEN)}}
\DoxyCodeLine{01597\ \textcolor{preprocessor}{\#endif}}
\DoxyCodeLine{01598\ \textcolor{preprocessor}{\#if\ defined(BDMA2)}}
\DoxyCodeLine{01599\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_BDMA2\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC-\/>AHB4ENR)\ \&=\ \string~\ (RCC\_AHB4ENR\_BDMA2EN)}}
\DoxyCodeLine{01600\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_BDMA\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_BDMA2\_CLK\_DISABLE()\ \ }\textcolor{comment}{/*\ for\ API\ backward\ compatibility*/}\textcolor{preprocessor}{}}
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\DoxyCodeLine{01605\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_ADC3\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ \ (RCC-\/>AHB4ENR)\ \&=\ \string~\ (RCC\_AHB4ENR\_ADC3EN)}}
\DoxyCodeLine{01606\ \textcolor{preprocessor}{\#endif}}
\DoxyCodeLine{01607\ \textcolor{preprocessor}{\#if\ defined(RCC\_AHB4ENR\_HSEMEN)}}
\DoxyCodeLine{01608\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_HSEM\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ \ (RCC-\/>AHB4ENR)\ \&=\ \string~\ (RCC\_AHB4ENR\_HSEMEN)}}
\DoxyCodeLine{01609\ \textcolor{preprocessor}{\#endif}}
\DoxyCodeLine{01610\ \textcolor{preprocessor}{\#if\ defined(RCC\_AHB4ENR\_SRDSRAMEN)}}
\DoxyCodeLine{01611\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_SRDSRAM\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ (RCC-\/>AHB4ENR)\ \&=\ \string~\ (RCC\_AHB4ENR\_SRDSRAMEN)}}
\DoxyCodeLine{01612\ \textcolor{preprocessor}{\#endif}}
\DoxyCodeLine{01613\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_BKPRAM\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ (RCC-\/>AHB4ENR)\ \&=\ \string~\ (RCC\_AHB4ENR\_BKPRAMEN)}}
\DoxyCodeLine{01614\ }
\DoxyCodeLine{01615\ }
\DoxyCodeLine{01621\ }
\DoxyCodeLine{01622\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_GPIOA\_IS\_CLK\_ENABLED()\ \ \ \ \ \ \ \ \ \ \ \ ((RCC-\/>AHB4ENR\ \&\ RCC\_AHB4ENR\_GPIOAEN)\ \ !=\ 0U)}}
\DoxyCodeLine{01623\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_GPIOB\_IS\_CLK\_ENABLED()\ \ \ \ \ \ \ \ \ \ \ \ ((RCC-\/>AHB4ENR\ \&\ RCC\_AHB4ENR\_GPIOBEN)\ \ !=\ 0U)}}
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\DoxyCodeLine{01625\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_GPIOD\_IS\_CLK\_ENABLED()\ \ \ \ \ \ \ \ \ \ \ \ ((RCC-\/>AHB4ENR\ \&\ RCC\_AHB4ENR\_GPIODEN)\ \ !=\ 0U)}}
\DoxyCodeLine{01626\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_GPIOE\_IS\_CLK\_ENABLED()\ \ \ \ \ \ \ \ \ \ \ \ ((RCC-\/>AHB4ENR\ \&\ RCC\_AHB4ENR\_GPIOEEN)\ \ !=\ 0U)}}
\DoxyCodeLine{01627\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_GPIOF\_IS\_CLK\_ENABLED()\ \ \ \ \ \ \ \ \ \ \ \ ((RCC-\/>AHB4ENR\ \&\ RCC\_AHB4ENR\_GPIOFEN)\ \ !=\ 0U)}}
\DoxyCodeLine{01628\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_GPIOG\_IS\_CLK\_ENABLED()\ \ \ \ \ \ \ \ \ \ \ \ ((RCC-\/>AHB4ENR\ \&\ RCC\_AHB4ENR\_GPIOGEN)\ \ !=\ 0U)}}
\DoxyCodeLine{01629\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_GPIOH\_IS\_CLK\_ENABLED()\ \ \ \ \ \ \ \ \ \ \ \ ((RCC-\/>AHB4ENR\ \&\ RCC\_AHB4ENR\_GPIOHEN)\ \ !=\ 0U)}}
\DoxyCodeLine{01630\ \textcolor{preprocessor}{\#if\ defined(GPIOI)}}
\DoxyCodeLine{01631\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_GPIOI\_IS\_CLK\_ENABLED()\ \ \ \ \ \ \ \ \ \ \ \ ((RCC-\/>AHB4ENR\ \&\ RCC\_AHB4ENR\_GPIOIEN)\ \ !=\ 0U)}}
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\DoxyCodeLine{01921\ }
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\DoxyCodeLine{01930\ \textcolor{preprocessor}{\#if\ defined(I2C5)}}
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\DoxyCodeLine{01938\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ I2C5\ */}\textcolor{preprocessor}{}}
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\DoxyCodeLine{01947\ }
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\DoxyCodeLine{01955\ }
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\DoxyCodeLine{01963\ }
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\DoxyCodeLine{02003\ }
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\DoxyCodeLine{02011\ }
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\DoxyCodeLine{02020\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ \ TIM23\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{02021\ }
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\DoxyCodeLine{02030\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ \ TIM24\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{02031\ }
\DoxyCodeLine{02032\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_TIM2\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC-\/>APB1LENR)\ \&=\ \string~\ (RCC\_APB1LENR\_TIM2EN)}}
\DoxyCodeLine{02033\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_TIM3\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC-\/>APB1LENR)\ \&=\ \string~\ (RCC\_APB1LENR\_TIM3EN)}}
\DoxyCodeLine{02034\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_TIM4\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC-\/>APB1LENR)\ \&=\ \string~\ (RCC\_APB1LENR\_TIM4EN)}}
\DoxyCodeLine{02035\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_TIM5\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC-\/>APB1LENR)\ \&=\ \string~\ (RCC\_APB1LENR\_TIM5EN)}}
\DoxyCodeLine{02036\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_TIM6\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC-\/>APB1LENR)\ \&=\ \string~\ (RCC\_APB1LENR\_TIM6EN)}}
\DoxyCodeLine{02037\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_TIM7\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC-\/>APB1LENR)\ \&=\ \string~\ (RCC\_APB1LENR\_TIM7EN)}}
\DoxyCodeLine{02038\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_TIM12\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ (RCC-\/>APB1LENR)\ \&=\ \string~\ (RCC\_APB1LENR\_TIM12EN)}}
\DoxyCodeLine{02039\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_TIM13\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ (RCC-\/>APB1LENR)\ \&=\ \string~\ (RCC\_APB1LENR\_TIM13EN)}}
\DoxyCodeLine{02040\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_TIM14\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ (RCC-\/>APB1LENR)\ \&=\ \string~\ (RCC\_APB1LENR\_TIM14EN)}}
\DoxyCodeLine{02041\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_LPTIM1\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ (RCC-\/>APB1LENR)\ \&=\ \string~\ (RCC\_APB1LENR\_LPTIM1EN)}}
\DoxyCodeLine{02042\ }
\DoxyCodeLine{02043\ \textcolor{preprocessor}{\#if\ defined(DUAL\_CORE)}}
\DoxyCodeLine{02044\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_WWDG2\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ (RCC-\/>APB1LENR)\ \&=\ \string~\ (RCC\_APB1LENR\_WWDG2EN)}}
\DoxyCodeLine{02045\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*DUAL\_CORE*/}\textcolor{preprocessor}{}}
\DoxyCodeLine{02046\ }
\DoxyCodeLine{02047\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_SPI2\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC-\/>APB1LENR)\ \&=\ \string~\ (RCC\_APB1LENR\_SPI2EN)}}
\DoxyCodeLine{02048\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_SPI3\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC-\/>APB1LENR)\ \&=\ \string~\ (RCC\_APB1LENR\_SPI3EN)}}
\DoxyCodeLine{02049\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_SPDIFRX\_CLK\_DISABLE()\ \ \ \ \ \ \ \ (RCC-\/>APB1LENR)\ \&=\ \string~\ (RCC\_APB1LENR\_SPDIFRXEN)}}
\DoxyCodeLine{02050\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_USART2\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ (RCC-\/>APB1LENR)\ \&=\ \string~\ (RCC\_APB1LENR\_USART2EN)}}
\DoxyCodeLine{02051\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_USART3\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ (RCC-\/>APB1LENR)\ \&=\ \string~\ (RCC\_APB1LENR\_USART3EN)}}
\DoxyCodeLine{02052\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_UART4\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ (RCC-\/>APB1LENR)\ \&=\ \string~\ (RCC\_APB1LENR\_UART4EN)}}
\DoxyCodeLine{02053\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_UART5\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ (RCC-\/>APB1LENR)\ \&=\ \string~\ (RCC\_APB1LENR\_UART5EN)}}
\DoxyCodeLine{02054\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_I2C1\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC-\/>APB1LENR)\ \&=\ \string~\ (RCC\_APB1LENR\_I2C1EN)}}
\DoxyCodeLine{02055\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_I2C2\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC-\/>APB1LENR)\ \&=\ \string~\ (RCC\_APB1LENR\_I2C2EN)}}
\DoxyCodeLine{02056\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_I2C3\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC-\/>APB1LENR)\ \&=\ \string~\ (RCC\_APB1LENR\_I2C3EN)}}
\DoxyCodeLine{02057\ \textcolor{preprocessor}{\#if\ defined(I2C5)}}
\DoxyCodeLine{02058\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_I2C5\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC-\/>APB1LENR)\ \&=\ \string~\ (RCC\_APB1LENR\_I2C5EN)}}
\DoxyCodeLine{02059\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ I2C5\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{02060\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_CEC\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ \ (RCC-\/>APB1LENR)\ \&=\ \string~\ (RCC\_APB1LENR\_CECEN)}}
\DoxyCodeLine{02061\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_DAC12\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ (RCC-\/>APB1LENR)\ \&=\ \string~\ (RCC\_APB1LENR\_DAC12EN)}}
\DoxyCodeLine{02062\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_UART7\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ (RCC-\/>APB1LENR)\ \&=\ \string~\ (RCC\_APB1LENR\_UART7EN)}}
\DoxyCodeLine{02063\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_UART8\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ (RCC-\/>APB1LENR)\ \&=\ \string~\ (RCC\_APB1LENR\_UART8EN)}}
\DoxyCodeLine{02064\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_CRS\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ \ (RCC-\/>APB1HENR)\ \&=\ \string~\ (RCC\_APB1HENR\_CRSEN)}}
\DoxyCodeLine{02065\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_SWPMI1\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ (RCC-\/>APB1HENR)\ \&=\ \string~\ (RCC\_APB1HENR\_SWPMIEN)}}
\DoxyCodeLine{02066\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_OPAMP\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ (RCC-\/>APB1HENR)\ \&=\ \string~\ (RCC\_APB1HENR\_OPAMPEN)}}
\DoxyCodeLine{02067\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_MDIOS\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ (RCC-\/>APB1HENR)\ \&=\ \string~\ (RCC\_APB1HENR\_MDIOSEN)}}
\DoxyCodeLine{02068\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_FDCAN\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ (RCC-\/>APB1HENR)\ \&=\ \string~\ (RCC\_APB1HENR\_FDCANEN)}}
\DoxyCodeLine{02069\ \textcolor{preprocessor}{\#if\ defined(TIM23)}}
\DoxyCodeLine{02070\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_TIM23\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ (RCC-\/>APB1HENR)\ \&=\ \string~\ (RCC\_APB1HENR\_TIM23EN)}}
\DoxyCodeLine{02071\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ TIM23\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{02072\ \textcolor{preprocessor}{\#if\ defined(TIM24)}}
\DoxyCodeLine{02073\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_TIM24\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ (RCC-\/>APB1HENR)\ \&=\ \string~\ (RCC\_APB1HENR\_TIM24EN)}}
\DoxyCodeLine{02074\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ TIM24\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{02075\ }
\DoxyCodeLine{02076\ }
\DoxyCodeLine{02082\ }
\DoxyCodeLine{02083\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_TIM2\_IS\_CLK\_ENABLED()\ \ \ \ \ \ \ \ \ \ \ \ ((RCC-\/>APB1LENR\ \&\ RCC\_APB1LENR\_TIM2EN)\ \ \ \ !=\ 0U)}}
\DoxyCodeLine{02084\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_TIM3\_IS\_CLK\_ENABLED()\ \ \ \ \ \ \ \ \ \ \ \ ((RCC-\/>APB1LENR\ \&\ RCC\_APB1LENR\_TIM3EN)\ \ \ \ !=\ 0U)}}
\DoxyCodeLine{02085\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_TIM4\_IS\_CLK\_ENABLED()\ \ \ \ \ \ \ \ \ \ \ \ ((RCC-\/>APB1LENR\ \&\ RCC\_APB1LENR\_TIM4EN)\ \ \ \ !=\ 0U)}}
\DoxyCodeLine{02086\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_TIM5\_IS\_CLK\_ENABLED()\ \ \ \ \ \ \ \ \ \ \ \ ((RCC-\/>APB1LENR\ \&\ RCC\_APB1LENR\_TIM5EN)\ \ \ \ !=\ 0U)}}
\DoxyCodeLine{02087\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_TIM6\_IS\_CLK\_ENABLED()\ \ \ \ \ \ \ \ \ \ \ \ ((RCC-\/>APB1LENR\ \&\ RCC\_APB1LENR\_TIM6EN)\ \ \ \ !=\ 0U)}}
\DoxyCodeLine{02088\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_TIM7\_IS\_CLK\_ENABLED()\ \ \ \ \ \ \ \ \ \ \ \ ((RCC-\/>APB1LENR\ \&\ RCC\_APB1LENR\_TIM7EN)\ \ \ \ !=\ 0U)}}
\DoxyCodeLine{02089\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_TIM12\_IS\_CLK\_ENABLED()\ \ \ \ \ \ \ \ \ \ \ ((RCC-\/>APB1LENR\ \&\ RCC\_APB1LENR\_TIM12EN)\ \ \ !=\ 0U)}}
\DoxyCodeLine{02090\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_TIM13\_IS\_CLK\_ENABLED()\ \ \ \ \ \ \ \ \ \ \ ((RCC-\/>APB1LENR\ \&\ RCC\_APB1LENR\_TIM13EN)\ \ \ !=\ 0U)}}
\DoxyCodeLine{02091\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_TIM14\_IS\_CLK\_ENABLED()\ \ \ \ \ \ \ \ \ \ \ ((RCC-\/>APB1LENR\ \&\ RCC\_APB1LENR\_TIM14EN)\ \ \ !=\ 0U)}}
\DoxyCodeLine{02092\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_LPTIM1\_IS\_CLK\_ENABLED()\ \ \ \ \ \ \ \ \ \ ((RCC-\/>APB1LENR\ \&\ RCC\_APB1LENR\_LPTIM1EN)\ \ !=\ 0U)}}
\DoxyCodeLine{02093\ \textcolor{preprocessor}{\#if\ defined(DUAL\_CORE)}}
\DoxyCodeLine{02094\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_WWDG2\_IS\_CLK\_ENABLED()\ \ \ \ \ \ \ \ \ \ \ ((RCC-\/>APB1LENR\ \&\ RCC\_APB1LENR\_WWDG2EN)\ \ \ !=\ 0U)}}
\DoxyCodeLine{02095\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*DUAL\_CORE*/}\textcolor{preprocessor}{}}
\DoxyCodeLine{02096\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_SPI2\_IS\_CLK\_ENABLED()\ \ \ \ \ \ \ \ \ \ \ \ ((RCC-\/>APB1LENR\ \&\ RCC\_APB1LENR\_SPI2EN)\ \ \ \ !=\ 0U)}}
\DoxyCodeLine{02097\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_SPI3\_IS\_CLK\_ENABLED()\ \ \ \ \ \ \ \ \ \ \ \ ((RCC-\/>APB1LENR\ \&\ RCC\_APB1LENR\_SPI3EN)\ \ \ \ !=\ 0U)}}
\DoxyCodeLine{02098\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_SPDIFRX\_IS\_CLK\_ENABLED()\ \ \ \ \ \ \ \ \ ((RCC-\/>APB1LENR\ \&\ RCC\_APB1LENR\_SPDIFRXEN)\ !=\ 0U)}}
\DoxyCodeLine{02099\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_USART2\_IS\_CLK\_ENABLED()\ \ \ \ \ \ \ \ \ \ ((RCC-\/>APB1LENR\ \&\ RCC\_APB1LENR\_USART2EN)\ \ !=\ 0U)}}
\DoxyCodeLine{02100\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_USART3\_IS\_CLK\_ENABLED()\ \ \ \ \ \ \ \ \ \ ((RCC-\/>APB1LENR\ \&\ RCC\_APB1LENR\_USART3EN)\ \ !=\ 0U)}}
\DoxyCodeLine{02101\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_UART4\_IS\_CLK\_ENABLED()\ \ \ \ \ \ \ \ \ \ \ ((RCC-\/>APB1LENR\ \&\ RCC\_APB1LENR\_UART4EN)\ \ \ !=\ 0U)}}
\DoxyCodeLine{02102\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_UART5\_IS\_CLK\_ENABLED()\ \ \ \ \ \ \ \ \ \ \ ((RCC-\/>APB1LENR\ \&\ RCC\_APB1LENR\_UART5EN)\ \ \ !=\ 0U)}}
\DoxyCodeLine{02103\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_I2C1\_IS\_CLK\_ENABLED()\ \ \ \ \ \ \ \ \ \ \ \ ((RCC-\/>APB1LENR\ \&\ RCC\_APB1LENR\_I2C1EN)\ \ \ \ !=\ 0U)}}
\DoxyCodeLine{02104\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_I2C2\_IS\_CLK\_ENABLED()\ \ \ \ \ \ \ \ \ \ \ \ ((RCC-\/>APB1LENR\ \&\ RCC\_APB1LENR\_I2C2EN)\ \ \ \ !=\ 0U)}}
\DoxyCodeLine{02105\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_I2C3\_IS\_CLK\_ENABLED()\ \ \ \ \ \ \ \ \ \ \ \ ((RCC-\/>APB1LENR\ \&\ RCC\_APB1LENR\_I2C3EN)\ \ \ \ !=\ 0U)}}
\DoxyCodeLine{02106\ \textcolor{preprocessor}{\#if\ defined(I2C5)}}
\DoxyCodeLine{02107\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_I2C5\_IS\_CLK\_ENABLED()\ \ \ \ \ \ \ \ \ \ \ \ ((RCC-\/>APB1LENR\ \&\ RCC\_APB1LENR\_I2C5EN)\ \ \ \ !=\ 0U)}}
\DoxyCodeLine{02108\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ I2C5\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{02109\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_CEC\_IS\_CLK\_ENABLED()\ \ \ \ \ \ \ \ \ \ \ \ \ ((RCC-\/>APB1LENR\ \&\ RCC\_APB1LENR\_CECEN)\ \ \ \ \ !=\ 0U)}}
\DoxyCodeLine{02110\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_DAC12\_IS\_CLK\_ENABLED()\ \ \ \ \ \ \ \ \ \ \ ((RCC-\/>APB1LENR\ \&\ RCC\_APB1LENR\_DAC12EN)\ \ \ !=\ 0U)}}
\DoxyCodeLine{02111\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_UART7\_IS\_CLK\_ENABLED()\ \ \ \ \ \ \ \ \ \ \ ((RCC-\/>APB1LENR\ \&\ RCC\_APB1LENR\_UART7EN)\ \ \ !=\ 0U)}}
\DoxyCodeLine{02112\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_UART8\_IS\_CLK\_ENABLED()\ \ \ \ \ \ \ \ \ \ \ ((RCC-\/>APB1LENR\ \&\ RCC\_APB1LENR\_UART8EN)\ \ \ !=\ 0U)}}
\DoxyCodeLine{02113\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_CRS\_IS\_CLK\_ENABLED()\ \ \ \ \ \ \ \ \ \ \ \ \ ((RCC-\/>APB1HENR\ \&\ RCC\_APB1HENR\_CRSEN)\ \ \ \ \ !=\ 0U)}}
\DoxyCodeLine{02114\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_SWPMI1\_IS\_CLK\_ENABLED()\ \ \ \ \ \ \ \ \ \ ((RCC-\/>APB1HENR\ \&\ RCC\_APB1HENR\_SWPMIEN)\ \ \ !=\ 0U)}}
\DoxyCodeLine{02115\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_OPAMP\_IS\_CLK\_ENABLED()\ \ \ \ \ \ \ \ \ \ \ ((RCC-\/>APB1HENR\ \&\ RCC\_APB1HENR\_OPAMPEN)\ \ \ !=\ 0U)}}
\DoxyCodeLine{02116\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_MDIOS\_IS\_CLK\_ENABLED()\ \ \ \ \ \ \ \ \ \ \ ((RCC-\/>APB1HENR\ \&\ RCC\_APB1HENR\_MDIOSEN)\ \ \ !=\ 0U)}}
\DoxyCodeLine{02117\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_FDCAN\_IS\_CLK\_ENABLED()\ \ \ \ \ \ \ \ \ \ \ ((RCC-\/>APB1HENR\ \&\ RCC\_APB1HENR\_FDCANEN)\ \ \ !=\ 0U)}}
\DoxyCodeLine{02118\ \textcolor{preprocessor}{\#if\ defined(TIM23)}}
\DoxyCodeLine{02119\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_TIM23\_IS\_CLK\_ENABLED()\ \ \ \ \ \ \ \ \ \ \ ((RCC-\/>APB1HENR\ \&\ RCC\_APB1HENR\_TIM23EN)\ \ \ !=\ 0U)}}
\DoxyCodeLine{02120\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ TIM23\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{02121\ \textcolor{preprocessor}{\#if\ defined(TIM24)}}
\DoxyCodeLine{02122\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_TIM24\_IS\_CLK\_ENABLED()\ \ \ \ \ \ \ \ \ \ \ ((RCC-\/>APB1HENR\ \&\ RCC\_APB1HENR\_TIM24EN)\ \ \ !=\ 0U)}}
\DoxyCodeLine{02123\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ TIM24\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{02124\ }
\DoxyCodeLine{02125\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_TIM2\_IS\_CLK\_DISABLED()\ \ \ \ \ \ \ \ \ \ \ ((RCC-\/>APB1LENR\ \&\ RCC\_APB1LENR\_TIM2EN)\ \ \ \ ==\ 0U)}}
\DoxyCodeLine{02126\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_TIM3\_IS\_CLK\_DISABLED()\ \ \ \ \ \ \ \ \ \ \ ((RCC-\/>APB1LENR\ \&\ RCC\_APB1LENR\_TIM3EN)\ \ \ \ ==\ 0U)}}
\DoxyCodeLine{02127\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_TIM4\_IS\_CLK\_DISABLED()\ \ \ \ \ \ \ \ \ \ \ ((RCC-\/>APB1LENR\ \&\ RCC\_APB1LENR\_TIM4EN)\ \ \ \ ==\ 0U)}}
\DoxyCodeLine{02128\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_TIM5\_IS\_CLK\_DISABLED()\ \ \ \ \ \ \ \ \ \ \ ((RCC-\/>APB1LENR\ \&\ RCC\_APB1LENR\_TIM5EN)\ \ \ \ ==\ 0U)}}
\DoxyCodeLine{02129\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_TIM6\_IS\_CLK\_DISABLED()\ \ \ \ \ \ \ \ \ \ \ ((RCC-\/>APB1LENR\ \&\ RCC\_APB1LENR\_TIM6EN)\ \ \ \ ==\ 0U)}}
\DoxyCodeLine{02130\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_TIM7\_IS\_CLK\_DISABLED()\ \ \ \ \ \ \ \ \ \ \ ((RCC-\/>APB1LENR\ \&\ RCC\_APB1LENR\_TIM7EN)\ \ \ \ ==\ 0U)}}
\DoxyCodeLine{02131\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_TIM12\_IS\_CLK\_DISABLED()\ \ \ \ \ \ \ \ \ \ ((RCC-\/>APB1LENR\ \&\ RCC\_APB1LENR\_TIM12EN)\ \ \ ==\ 0U)}}
\DoxyCodeLine{02132\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_TIM13\_IS\_CLK\_DISABLED()\ \ \ \ \ \ \ \ \ \ ((RCC-\/>APB1LENR\ \&\ RCC\_APB1LENR\_TIM13EN)\ \ \ ==\ 0U)}}
\DoxyCodeLine{02133\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_TIM14\_IS\_CLK\_DISABLED()\ \ \ \ \ \ \ \ \ \ ((RCC-\/>APB1LENR\ \&\ RCC\_APB1LENR\_TIM14EN)\ \ \ ==\ 0U)}}
\DoxyCodeLine{02134\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_LPTIM1\_IS\_CLK\_DISABLED()\ \ \ \ \ \ \ \ \ ((RCC-\/>APB1LENR\ \&\ RCC\_APB1LENR\_LPTIM1EN)\ \ ==\ 0U)}}
\DoxyCodeLine{02135\ \textcolor{preprocessor}{\#if\ defined(DUAL\_CORE)}}
\DoxyCodeLine{02136\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_WWDG2\_IS\_CLK\_DISABLED()\ \ \ \ \ \ \ \ \ \ ((RCC-\/>APB1LENR\ \&\ RCC\_APB1LENR\_WWDG2EN)\ \ \ ==\ 0U)}}
\DoxyCodeLine{02137\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*DUAL\_CORE*/}\textcolor{preprocessor}{}}
\DoxyCodeLine{02138\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_SPI2\_IS\_CLK\_DISABLED()\ \ \ \ \ \ \ \ \ \ \ ((RCC-\/>APB1LENR\ \&\ RCC\_APB1LENR\_SPI2EN)\ \ \ \ ==\ 0U)}}
\DoxyCodeLine{02139\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_SPI3\_IS\_CLK\_DISABLED()\ \ \ \ \ \ \ \ \ \ \ ((RCC-\/>APB1LENR\ \&\ RCC\_APB1LENR\_SPI3EN)\ \ \ \ ==\ 0U)}}
\DoxyCodeLine{02140\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_SPDIFRX\_IS\_CLK\_DISABLED()\ \ \ \ \ \ \ \ ((RCC-\/>APB1LENR\ \&\ RCC\_APB1LENR\_SPDIFRXEN)\ ==\ 0U)}}
\DoxyCodeLine{02141\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_USART2\_IS\_CLK\_DISABLED()\ \ \ \ \ \ \ \ \ ((RCC-\/>APB1LENR\ \&\ RCC\_APB1LENR\_USART2EN)\ \ ==\ 0U)}}
\DoxyCodeLine{02142\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_USART3\_IS\_CLK\_DISABLED()\ \ \ \ \ \ \ \ \ ((RCC-\/>APB1LENR\ \&\ RCC\_APB1LENR\_USART3EN)\ \ ==\ 0U)}}
\DoxyCodeLine{02143\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_UART4\_IS\_CLK\_DISABLED()\ \ \ \ \ \ \ \ \ \ ((RCC-\/>APB1LENR\ \&\ RCC\_APB1LENR\_UART4EN)\ \ \ ==\ 0U)}}
\DoxyCodeLine{02144\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_UART5\_IS\_CLK\_DISABLED()\ \ \ \ \ \ \ \ \ \ ((RCC-\/>APB1LENR\ \&\ RCC\_APB1LENR\_UART5EN)\ \ \ ==\ 0U)}}
\DoxyCodeLine{02145\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_I2C1\_IS\_CLK\_DISABLED()\ \ \ \ \ \ \ \ \ \ \ ((RCC-\/>APB1LENR\ \&\ RCC\_APB1LENR\_I2C1EN)\ \ \ \ ==\ 0U)}}
\DoxyCodeLine{02146\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_I2C2\_IS\_CLK\_DISABLED()\ \ \ \ \ \ \ \ \ \ \ ((RCC-\/>APB1LENR\ \&\ RCC\_APB1LENR\_I2C2EN)\ \ \ \ ==\ 0U)}}
\DoxyCodeLine{02147\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_I2C3\_IS\_CLK\_DISABLED()\ \ \ \ \ \ \ \ \ \ \ ((RCC-\/>APB1LENR\ \&\ RCC\_APB1LENR\_I2C3EN)\ \ \ \ ==\ 0U)}}
\DoxyCodeLine{02148\ \textcolor{preprocessor}{\#if\ defined(I2C5)}}
\DoxyCodeLine{02149\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_I2C5\_IS\_CLK\_DISABLED()\ \ \ \ \ \ \ \ \ \ \ ((RCC-\/>APB1LENR\ \&\ RCC\_APB1LENR\_I2C5EN)\ \ \ \ ==\ 0U)}}
\DoxyCodeLine{02150\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ I2C5\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{02151\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_CEC\_IS\_CLK\_DISABLED()\ \ \ \ \ \ \ \ \ \ \ \ ((RCC-\/>APB1LENR\ \&\ RCC\_APB1LENR\_CECEN)\ \ \ \ \ ==\ 0U)}}
\DoxyCodeLine{02152\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_DAC12\_IS\_CLK\_DISABLED()\ \ \ \ \ \ \ \ \ \ ((RCC-\/>APB1LENR\ \&\ RCC\_APB1LENR\_DAC12EN)\ \ \ ==\ 0U)}}
\DoxyCodeLine{02153\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_UART7\_IS\_CLK\_DISABLED()\ \ \ \ \ \ \ \ \ \ ((RCC-\/>APB1LENR\ \&\ RCC\_APB1LENR\_UART7EN)\ \ \ ==\ 0U)}}
\DoxyCodeLine{02154\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_UART8\_IS\_CLK\_DISABLED()\ \ \ \ \ \ \ \ \ \ ((RCC-\/>APB1LENR\ \&\ RCC\_APB1LENR\_UART8EN)\ \ \ ==\ 0U)}}
\DoxyCodeLine{02155\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_CRS\_IS\_CLK\_DISABLED()\ \ \ \ \ \ \ \ \ \ \ \ ((RCC-\/>APB1HENR\ \&\ RCC\_APB1HENR\_CRSEN)\ \ \ \ \ ==\ 0U)}}
\DoxyCodeLine{02156\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_SWPMI1\_IS\_CLK\_DISABLED()\ \ \ \ \ \ \ \ \ ((RCC-\/>APB1HENR\ \&\ RCC\_APB1HENR\_SWPMIEN)\ \ \ ==\ 0U)}}
\DoxyCodeLine{02157\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_OPAMP\_IS\_CLK\_DISABLED()\ \ \ \ \ \ \ \ \ \ ((RCC-\/>APB1HENR\ \&\ RCC\_APB1HENR\_OPAMPEN)\ \ \ ==\ 0U)}}
\DoxyCodeLine{02158\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_MDIOS\_IS\_CLK\_DISABLED()\ \ \ \ \ \ \ \ \ \ ((RCC-\/>APB1HENR\ \&\ RCC\_APB1HENR\_MDIOSEN)\ \ \ ==\ 0U)}}
\DoxyCodeLine{02159\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_FDCAN\_IS\_CLK\_DISABLED()\ \ \ \ \ \ \ \ \ \ ((RCC-\/>APB1HENR\ \&\ RCC\_APB1HENR\_FDCANEN)\ \ \ ==\ 0U)}}
\DoxyCodeLine{02160\ \textcolor{preprocessor}{\#if\ defined(TIM23)}}
\DoxyCodeLine{02161\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_TIM23\_IS\_CLK\_DISABLED()\ \ \ \ \ \ \ \ \ \ ((RCC-\/>APB1HENR\ \&\ RCC\_APB1HENR\_TIM23EN)\ \ \ ==\ 0U)}}
\DoxyCodeLine{02162\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ TIM23\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{02163\ \textcolor{preprocessor}{\#if\ defined(TIM24)}}
\DoxyCodeLine{02164\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_TIM24\_IS\_CLK\_DISABLED()\ \ \ \ \ \ \ \ \ \ ((RCC-\/>APB1HENR\ \&\ RCC\_APB1HENR\_TIM24EN)\ \ \ ==\ 0U)}}
\DoxyCodeLine{02165\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ TIM24\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{02166\ }
\DoxyCodeLine{02167\ }
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\DoxyCodeLine{02181\ }
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\DoxyCodeLine{02189\ }
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\DoxyCodeLine{02197\ }
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\DoxyCodeLine{02205\ }
\DoxyCodeLine{02206\ \textcolor{preprocessor}{\#if\ defined(UART9)}}
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\DoxyCodeLine{02214\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*UART9*/}\textcolor{preprocessor}{}}
\DoxyCodeLine{02215\ }
\DoxyCodeLine{02216\ \textcolor{preprocessor}{\#if\ defined(USART10)}}
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\DoxyCodeLine{02224\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*USART10*/}\textcolor{preprocessor}{}}
\DoxyCodeLine{02225\ }
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\DoxyCodeLine{02233\ }
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\DoxyCodeLine{02241\ }
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\DoxyCodeLine{02249\ }
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\DoxyCodeLine{02257\ }
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\DoxyCodeLine{02265\ }
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\DoxyCodeLine{02273\ }
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\DoxyCodeLine{02281\ }
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\DoxyCodeLine{02431\ }
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\DoxyCodeLine{02435\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ an\ RCC\ peripheral\ clock\ enabling\ */}\textcolor{preprocessor}{\ \(\backslash\)}}
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\DoxyCodeLine{02439\ }
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\DoxyCodeLine{02445\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ UNUSED(tmpreg);\ \(\backslash\)}}
\DoxyCodeLine{02446\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ while(0)}}
\DoxyCodeLine{02447\ }
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\DoxyCodeLine{02450\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC-\/>APB4ENR,\ RCC\_APB4ENR\_LPTIM2EN);\(\backslash\)}}
\DoxyCodeLine{02451\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ an\ RCC\ peripheral\ clock\ enabling\ */}\textcolor{preprocessor}{\ \(\backslash\)}}
\DoxyCodeLine{02452\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC-\/>APB4ENR,\ RCC\_APB4ENR\_LPTIM2EN);\(\backslash\)}}
\DoxyCodeLine{02453\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ UNUSED(tmpreg);\ \(\backslash\)}}
\DoxyCodeLine{02454\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ while(0)}}
\DoxyCodeLine{02455\ }
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\DoxyCodeLine{02457\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_IO\ uint32\_t\ tmpreg;\ \(\backslash\)}}
\DoxyCodeLine{02458\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC-\/>APB4ENR,\ RCC\_APB4ENR\_LPTIM3EN);\(\backslash\)}}
\DoxyCodeLine{02459\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ an\ RCC\ peripheral\ clock\ enabling\ */}\textcolor{preprocessor}{\ \(\backslash\)}}
\DoxyCodeLine{02460\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC-\/>APB4ENR,\ RCC\_APB4ENR\_LPTIM3EN);\(\backslash\)}}
\DoxyCodeLine{02461\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ UNUSED(tmpreg);\ \(\backslash\)}}
\DoxyCodeLine{02462\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ while(0)}}
\DoxyCodeLine{02463\ }
\DoxyCodeLine{02464\ \textcolor{preprocessor}{\#if\ defined(LPTIM4)}}
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\DoxyCodeLine{02466\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_IO\ uint32\_t\ tmpreg;\ \(\backslash\)}}
\DoxyCodeLine{02467\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC-\/>APB4ENR,\ RCC\_APB4ENR\_LPTIM4EN);\(\backslash\)}}
\DoxyCodeLine{02468\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ an\ RCC\ peripheral\ clock\ enabling\ */}\textcolor{preprocessor}{\ \(\backslash\)}}
\DoxyCodeLine{02469\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC-\/>APB4ENR,\ RCC\_APB4ENR\_LPTIM4EN);\(\backslash\)}}
\DoxyCodeLine{02470\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ UNUSED(tmpreg);\ \(\backslash\)}}
\DoxyCodeLine{02471\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ while(0)}}
\DoxyCodeLine{02472\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ LPTIM4\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{02473\ }
\DoxyCodeLine{02474\ \textcolor{preprocessor}{\#if\ defined(LPTIM5)}}
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\DoxyCodeLine{02477\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC-\/>APB4ENR,\ RCC\_APB4ENR\_LPTIM5EN);\(\backslash\)}}
\DoxyCodeLine{02478\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ an\ RCC\ peripheral\ clock\ enabling\ */}\textcolor{preprocessor}{\ \(\backslash\)}}
\DoxyCodeLine{02479\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC-\/>APB4ENR,\ RCC\_APB4ENR\_LPTIM5EN);\(\backslash\)}}
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\DoxyCodeLine{02482\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ LPTIM5\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{02483\ }
\DoxyCodeLine{02484\ \textcolor{preprocessor}{\#if\ defined(DAC2)}}
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\DoxyCodeLine{02492\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ \ DAC2\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{02493\ }
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\DoxyCodeLine{02500\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ while(0)}}
\DoxyCodeLine{02501\ }
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\DoxyCodeLine{02504\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC-\/>APB4ENR,\ RCC\_APB4ENR\_VREFEN);\(\backslash\)}}
\DoxyCodeLine{02505\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ an\ RCC\ peripheral\ clock\ enabling\ */}\textcolor{preprocessor}{\ \(\backslash\)}}
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\DoxyCodeLine{02508\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ while(0)}}
\DoxyCodeLine{02509\ }
\DoxyCodeLine{02510\ \textcolor{preprocessor}{\#if\ defined(SAI4)}}
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\DoxyCodeLine{02515\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC-\/>APB4ENR,\ RCC\_APB4ENR\_SAI4EN);\(\backslash\)}}
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\DoxyCodeLine{02517\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ while(0)}}
\DoxyCodeLine{02518\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ SAI4\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{02519\ }
\DoxyCodeLine{02520\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_RTC\_CLK\_ENABLE()\ \ \ do\ \{\ \(\backslash\)}}
\DoxyCodeLine{02521\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_IO\ uint32\_t\ tmpreg;\ \(\backslash\)}}
\DoxyCodeLine{02522\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC-\/>APB4ENR,\ RCC\_APB4ENR\_RTCAPBEN);\(\backslash\)}}
\DoxyCodeLine{02523\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ an\ RCC\ peripheral\ clock\ enabling\ */}\textcolor{preprocessor}{\ \(\backslash\)}}
\DoxyCodeLine{02524\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC-\/>APB4ENR,\ RCC\_APB4ENR\_RTCAPBEN);\(\backslash\)}}
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\DoxyCodeLine{02526\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ while(0)}}
\DoxyCodeLine{02527\ }
\DoxyCodeLine{02528\ \textcolor{preprocessor}{\#if\ defined(DTS)}}
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\DoxyCodeLine{02536\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*DTS*/}\textcolor{preprocessor}{}}
\DoxyCodeLine{02537\ }
\DoxyCodeLine{02538\ \textcolor{preprocessor}{\#if\ defined(DFSDM2\_BASE)}}
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\DoxyCodeLine{02546\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*DFSDM2*/}\textcolor{preprocessor}{}}
\DoxyCodeLine{02547\ }
\DoxyCodeLine{02548\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_SYSCFG\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC-\/>APB4ENR)\ \&=\ \string~\ (RCC\_APB4ENR\_SYSCFGEN)}}
\DoxyCodeLine{02549\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_LPUART1\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ (RCC-\/>APB4ENR)\ \&=\ \string~\ (RCC\_APB4ENR\_LPUART1EN)}}
\DoxyCodeLine{02550\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_SPI6\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ \ \ (RCC-\/>APB4ENR)\ \&=\ \string~\ (RCC\_APB4ENR\_SPI6EN)}}
\DoxyCodeLine{02551\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_I2C4\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ \ \ (RCC-\/>APB4ENR)\ \&=\ \string~\ (RCC\_APB4ENR\_I2C4EN)}}
\DoxyCodeLine{02552\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_LPTIM2\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC-\/>APB4ENR)\ \&=\ \string~\ (RCC\_APB4ENR\_LPTIM2EN)}}
\DoxyCodeLine{02553\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_LPTIM3\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC-\/>APB4ENR)\ \&=\ \string~\ (RCC\_APB4ENR\_LPTIM3EN)}}
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\DoxyCodeLine{02636\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*DFSDM2*/}\textcolor{preprocessor}{}}
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\DoxyCodeLine{02638\ \textcolor{preprocessor}{\#if\ defined(DUAL\_CORE)}}
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\DoxyCodeLine{02640\ \textcolor{comment}{/*\ Exported\ macros\ for\ RCC\_C1\ -\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/*/}}
\DoxyCodeLine{02641\ }
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\DoxyCodeLine{02701\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_DMA2D\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>AHB3ENR\ \&=\ \string~\ (RCC\_AHB3ENR\_DMA2DEN))}}
\DoxyCodeLine{02702\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_JPGDECEN\_CLK\_DISABLE()\ \ \ \ \ \ \ \ (RCC\_C1-\/>AHB3ENR\ \&=\ \string~\ (RCC\_AHB3ENR\_JPGDECEN))}}
\DoxyCodeLine{02703\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_FMC\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>AHB3ENR\ \&=\ \string~\ (RCC\_AHB3ENR\_FMCEN))}}
\DoxyCodeLine{02704\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_QSPI\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>AHB3ENR\ \&=\ \string~\ (RCC\_AHB3ENR\_QSPIEN))}}
\DoxyCodeLine{02705\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_SDMMC1\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>AHB3ENR\ \&=\ \string~\ (RCC\_AHB3ENR\_SDMMC1EN))}}
\DoxyCodeLine{02706\ }
\DoxyCodeLine{02707\ }
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\DoxyCodeLine{02709\ }
\DoxyCodeLine{02715\ }
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\DoxyCodeLine{02723\ }
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\DoxyCodeLine{02731\ }
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\DoxyCodeLine{02739\ }
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\DoxyCodeLine{02743\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ an\ RCC\ peripheral\ clock\ enabling\ */}\textcolor{preprocessor}{\ \(\backslash\)}}
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\DoxyCodeLine{02747\ }
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\DoxyCodeLine{02755\ }
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\DoxyCodeLine{02805\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_DMA1\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>AHB1ENR\ \&=\ \string~\ (RCC\_AHB1ENR\_DMA1EN))}}
\DoxyCodeLine{02806\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_DMA2\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>AHB1ENR\ \&=\ \string~\ (RCC\_AHB1ENR\_DMA2EN))}}
\DoxyCodeLine{02807\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_ADC12\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>AHB1ENR\ \&=\ \string~\ (RCC\_AHB1ENR\_ADC12EN))}}
\DoxyCodeLine{02808\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_ART\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>AHB1ENR\ \&=\ \string~\ (RCC\_AHB1ENR\_ARTEN))}}
\DoxyCodeLine{02809\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_ETH1MAC\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>AHB1ENR\ \&=\ \string~\ (RCC\_AHB1ENR\_ETH1MACEN))}}
\DoxyCodeLine{02810\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_ETH1TX\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>AHB1ENR\ \&=\ \string~\ (RCC\_AHB1ENR\_ETH1TXEN))}}
\DoxyCodeLine{02811\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_ETH1RX\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>AHB1ENR\ \&=\ \string~\ (RCC\_AHB1ENR\_ETH1RXEN))}}
\DoxyCodeLine{02812\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_USB1\_OTG\_HS\_CLK\_DISABLE()\ \ \ \ \ \ (RCC\_C1-\/>AHB1ENR\ \&=\ \string~\ (RCC\_AHB1ENR\_USB1OTGHSEN))}}
\DoxyCodeLine{02813\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_USB1\_OTG\_HS\_ULPI\_CLK\_DISABLE()\ (RCC\_C1-\/>AHB1ENR\ \&=\ \string~\ (RCC\_AHB1ENR\_USB1OTGHSULPIEN))}}
\DoxyCodeLine{02814\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_USB2\_OTG\_FS\_CLK\_DISABLE()\ \ \ \ \ \ (RCC\_C1-\/>AHB1ENR\ \&=\ \string~\ (RCC\_AHB1ENR\_USB2OTGHSEN))}}
\DoxyCodeLine{02815\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_USB2\_OTG\_FS\_ULPI\_CLK\_DISABLE()\ (RCC\_C1-\/>AHB1ENR\ \&=\ \string~\ (RCC\_AHB1ENR\_USB2OTGHSULPIEN))}}
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\DoxyCodeLine{02830\ \textcolor{preprocessor}{\#if\ defined(CRYP)}}
\DoxyCodeLine{02831\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_CRYP\_CLK\_ENABLE()\ \ \ do\ \{\ \(\backslash\)}}
\DoxyCodeLine{02832\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_IO\ uint32\_t\ tmpreg;\ \(\backslash\)}}
\DoxyCodeLine{02833\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC\_C1-\/>AHB2ENR,\ RCC\_AHB2ENR\_CRYPEN);\(\backslash\)}}
\DoxyCodeLine{02834\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ an\ RCC\ peripheral\ clock\ enabling\ */}\textcolor{preprocessor}{\ \(\backslash\)}}
\DoxyCodeLine{02835\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC\_C1-\/>AHB2ENR,\ RCC\_AHB2ENR\_CRYPEN);\(\backslash\)}}
\DoxyCodeLine{02836\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ UNUSED(tmpreg);\ \(\backslash\)}}
\DoxyCodeLine{02837\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ while(0)}}
\DoxyCodeLine{02838\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ CRYP\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{02839\ }
\DoxyCodeLine{02840\ \textcolor{preprocessor}{\#if\ defined(HASH)}}
\DoxyCodeLine{02841\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_HASH\_CLK\_ENABLE()\ \ \ do\ \{\ \(\backslash\)}}
\DoxyCodeLine{02842\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_IO\ uint32\_t\ tmpreg;\ \(\backslash\)}}
\DoxyCodeLine{02843\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC\_C1-\/>AHB2ENR,\ RCC\_AHB2ENR\_HASHEN);\(\backslash\)}}
\DoxyCodeLine{02844\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ an\ RCC\ peripheral\ clock\ enabling\ */}\textcolor{preprocessor}{\ \(\backslash\)}}
\DoxyCodeLine{02845\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC\_C1-\/>AHB2ENR,\ RCC\_AHB2ENR\_HASHEN);\(\backslash\)}}
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\DoxyCodeLine{02847\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ while(0)}}
\DoxyCodeLine{02848\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ HASH\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{02849\ }
\DoxyCodeLine{02850\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_RNG\_CLK\_ENABLE()\ \ \ do\ \{\ \(\backslash\)}}
\DoxyCodeLine{02851\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_IO\ uint32\_t\ tmpreg;\ \(\backslash\)}}
\DoxyCodeLine{02852\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC\_C1-\/>AHB2ENR,\ RCC\_AHB2ENR\_RNGEN);\(\backslash\)}}
\DoxyCodeLine{02853\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ an\ RCC\ peripheral\ clock\ enabling\ */}\textcolor{preprocessor}{\ \(\backslash\)}}
\DoxyCodeLine{02854\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC\_C1-\/>AHB2ENR,\ RCC\_AHB2ENR\_RNGEN);\(\backslash\)}}
\DoxyCodeLine{02855\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ UNUSED(tmpreg);\ \(\backslash\)}}
\DoxyCodeLine{02856\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ while(0)}}
\DoxyCodeLine{02857\ }
\DoxyCodeLine{02858\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_SDMMC2\_CLK\_ENABLE()\ \ \ do\ \{\ \(\backslash\)}}
\DoxyCodeLine{02859\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_IO\ uint32\_t\ tmpreg;\ \(\backslash\)}}
\DoxyCodeLine{02860\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC\_C1-\/>AHB2ENR,\ RCC\_AHB2ENR\_SDMMC2EN);\(\backslash\)}}
\DoxyCodeLine{02861\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ an\ RCC\ peripheral\ clock\ enabling\ */}\textcolor{preprocessor}{\ \(\backslash\)}}
\DoxyCodeLine{02862\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC\_C1-\/>AHB2ENR,\ RCC\_AHB2ENR\_SDMMC2EN);\(\backslash\)}}
\DoxyCodeLine{02863\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ UNUSED(tmpreg);\ \(\backslash\)}}
\DoxyCodeLine{02864\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ while(0)}}
\DoxyCodeLine{02865\ }
\DoxyCodeLine{02866\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_D2SRAM1\_CLK\_ENABLE()\ \ \ do\ \{\ \(\backslash\)}}
\DoxyCodeLine{02867\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_IO\ uint32\_t\ tmpreg;\ \(\backslash\)}}
\DoxyCodeLine{02868\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC\_C1-\/>AHB2ENR,\ RCC\_AHB2ENR\_D2SRAM1EN);\(\backslash\)}}
\DoxyCodeLine{02869\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ an\ RCC\ peripheral\ clock\ enabling\ */}\textcolor{preprocessor}{\ \(\backslash\)}}
\DoxyCodeLine{02870\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC\_C1-\/>AHB2ENR,\ RCC\_AHB2ENR\_D2SRAM1EN);\(\backslash\)}}
\DoxyCodeLine{02871\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ UNUSED(tmpreg);\ \(\backslash\)}}
\DoxyCodeLine{02872\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ while(0)}}
\DoxyCodeLine{02873\ }
\DoxyCodeLine{02874\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_D2SRAM2\_CLK\_ENABLE()\ \ \ do\ \{\ \(\backslash\)}}
\DoxyCodeLine{02875\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_IO\ uint32\_t\ tmpreg;\ \(\backslash\)}}
\DoxyCodeLine{02876\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC\_C1-\/>AHB2ENR,\ RCC\_AHB2ENR\_D2SRAM2EN);\(\backslash\)}}
\DoxyCodeLine{02877\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ an\ RCC\ peripheral\ clock\ enabling\ */}\textcolor{preprocessor}{\ \(\backslash\)}}
\DoxyCodeLine{02878\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC\_C1-\/>AHB2ENR,\ RCC\_AHB2ENR\_D2SRAM2EN);\(\backslash\)}}
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\DoxyCodeLine{02880\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ while(0)}}
\DoxyCodeLine{02881\ }
\DoxyCodeLine{02882\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_D2SRAM3\_CLK\_ENABLE()\ \ \ do\ \{\ \(\backslash\)}}
\DoxyCodeLine{02883\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_IO\ uint32\_t\ tmpreg;\ \(\backslash\)}}
\DoxyCodeLine{02884\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC\_C1-\/>AHB2ENR,\ RCC\_AHB2ENR\_D2SRAM3EN);\(\backslash\)}}
\DoxyCodeLine{02885\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ an\ RCC\ peripheral\ clock\ enabling\ */}\textcolor{preprocessor}{\ \(\backslash\)}}
\DoxyCodeLine{02886\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC\_C1-\/>AHB2ENR,\ RCC\_AHB2ENR\_D2SRAM3EN);\(\backslash\)}}
\DoxyCodeLine{02887\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ UNUSED(tmpreg);\ \(\backslash\)}}
\DoxyCodeLine{02888\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ while(0)}}
\DoxyCodeLine{02889\ }
\DoxyCodeLine{02890\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_DCMI\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>AHB2ENR\ \&=\ \string~\ (RCC\_AHB2ENR\_DCMIEN))}}
\DoxyCodeLine{02891\ \textcolor{preprocessor}{\#if\ defined(CRYP)}}
\DoxyCodeLine{02892\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_CRYP\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>AHB2ENR\ \&=\ \string~\ (RCC\_AHB2ENR\_CRYPEN))}}
\DoxyCodeLine{02893\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ CRYP\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{02894\ \textcolor{preprocessor}{\#if\ defined(HASH)}}
\DoxyCodeLine{02895\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_HASH\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>AHB2ENR\ \&=\ \string~\ (RCC\_AHB2ENR\_HASHEN))}}
\DoxyCodeLine{02896\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ HASH\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{02897\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_RNG\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>AHB2ENR\ \&=\ \string~\ (RCC\_AHB2ENR\_RNGEN))}}
\DoxyCodeLine{02898\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_SDMMC2\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>AHB2ENR\ \&=\ \string~\ (RCC\_AHB2ENR\_SDMMC2EN))}}
\DoxyCodeLine{02899\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_D2SRAM1\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>AHB2ENR\ \&=\ \string~\ (RCC\_AHB2ENR\_D2SRAM1EN))}}
\DoxyCodeLine{02900\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_D2SRAM2\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>AHB2ENR\ \&=\ \string~\ (RCC\_AHB2ENR\_D2SRAM2EN))}}
\DoxyCodeLine{02901\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_D2SRAM3\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>AHB2ENR\ \&=\ \string~\ (RCC\_AHB2ENR\_D2SRAM3EN))}}
\DoxyCodeLine{02902\ }
\DoxyCodeLine{02908\ }
\DoxyCodeLine{02909\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_GPIOA\_CLK\_ENABLE()\ \ \ do\ \{\ \(\backslash\)}}
\DoxyCodeLine{02910\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_IO\ uint32\_t\ tmpreg;\ \(\backslash\)}}
\DoxyCodeLine{02911\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC\_C1-\/>AHB4ENR,\ RCC\_AHB4ENR\_GPIOAEN);\(\backslash\)}}
\DoxyCodeLine{02912\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ an\ RCC\ peripheral\ clock\ enabling\ */}\textcolor{preprocessor}{\ \(\backslash\)}}
\DoxyCodeLine{02913\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC\_C1-\/>AHB4ENR,\ RCC\_AHB4ENR\_GPIOAEN);\(\backslash\)}}
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\DoxyCodeLine{02915\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ while(0)}}
\DoxyCodeLine{02916\ }
\DoxyCodeLine{02917\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_GPIOB\_CLK\_ENABLE()\ \ \ do\ \{\ \(\backslash\)}}
\DoxyCodeLine{02918\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_IO\ uint32\_t\ tmpreg;\ \(\backslash\)}}
\DoxyCodeLine{02919\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC\_C1-\/>AHB4ENR,\ RCC\_AHB4ENR\_GPIOBEN);\(\backslash\)}}
\DoxyCodeLine{02920\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ an\ RCC\ peripheral\ clock\ enabling\ */}\textcolor{preprocessor}{\ \(\backslash\)}}
\DoxyCodeLine{02921\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC\_C1-\/>AHB4ENR,\ RCC\_AHB4ENR\_GPIOBEN);\(\backslash\)}}
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\DoxyCodeLine{02923\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ while(0)}}
\DoxyCodeLine{02924\ }
\DoxyCodeLine{02925\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_GPIOC\_CLK\_ENABLE()\ \ \ do\ \{\ \(\backslash\)}}
\DoxyCodeLine{02926\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_IO\ uint32\_t\ tmpreg;\ \(\backslash\)}}
\DoxyCodeLine{02927\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC\_C1-\/>AHB4ENR,\ RCC\_AHB4ENR\_GPIOCEN);\(\backslash\)}}
\DoxyCodeLine{02928\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ an\ RCC\ peripheral\ clock\ enabling\ */}\textcolor{preprocessor}{\ \(\backslash\)}}
\DoxyCodeLine{02929\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC\_C1-\/>AHB4ENR,\ RCC\_AHB4ENR\_GPIOCEN);\(\backslash\)}}
\DoxyCodeLine{02930\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ UNUSED(tmpreg);\ \(\backslash\)}}
\DoxyCodeLine{02931\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ while(0)}}
\DoxyCodeLine{02932\ }
\DoxyCodeLine{02933\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_GPIOD\_CLK\_ENABLE()\ \ \ do\ \{\ \(\backslash\)}}
\DoxyCodeLine{02934\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_IO\ uint32\_t\ tmpreg;\ \(\backslash\)}}
\DoxyCodeLine{02935\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC\_C1-\/>AHB4ENR,\ RCC\_AHB4ENR\_GPIODEN);\(\backslash\)}}
\DoxyCodeLine{02936\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ an\ RCC\ peripheral\ clock\ enabling\ */}\textcolor{preprocessor}{\ \(\backslash\)}}
\DoxyCodeLine{02937\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC\_C1-\/>AHB4ENR,\ RCC\_AHB4ENR\_GPIODEN);\(\backslash\)}}
\DoxyCodeLine{02938\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ UNUSED(tmpreg);\ \(\backslash\)}}
\DoxyCodeLine{02939\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ while(0)}}
\DoxyCodeLine{02940\ }
\DoxyCodeLine{02941\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_GPIOE\_CLK\_ENABLE()\ \ \ do\ \{\ \(\backslash\)}}
\DoxyCodeLine{02942\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_IO\ uint32\_t\ tmpreg;\ \(\backslash\)}}
\DoxyCodeLine{02943\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC\_C1-\/>AHB4ENR,\ RCC\_AHB4ENR\_GPIOEEN);\(\backslash\)}}
\DoxyCodeLine{02944\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ an\ RCC\ peripheral\ clock\ enabling\ */}\textcolor{preprocessor}{\ \(\backslash\)}}
\DoxyCodeLine{02945\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC\_C1-\/>AHB4ENR,\ RCC\_AHB4ENR\_GPIOEEN);\(\backslash\)}}
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\DoxyCodeLine{02947\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ while(0)}}
\DoxyCodeLine{02948\ }
\DoxyCodeLine{02949\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_GPIOF\_CLK\_ENABLE()\ \ \ do\ \{\ \(\backslash\)}}
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\DoxyCodeLine{02951\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC\_C1-\/>AHB4ENR,\ RCC\_AHB4ENR\_GPIOFEN);\(\backslash\)}}
\DoxyCodeLine{02952\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ an\ RCC\ peripheral\ clock\ enabling\ */}\textcolor{preprocessor}{\ \(\backslash\)}}
\DoxyCodeLine{02953\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC\_C1-\/>AHB4ENR,\ RCC\_AHB4ENR\_GPIOFEN);\(\backslash\)}}
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\DoxyCodeLine{02955\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ while(0)}}
\DoxyCodeLine{02956\ }
\DoxyCodeLine{02957\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_GPIOG\_CLK\_ENABLE()\ \ \ do\ \{\ \(\backslash\)}}
\DoxyCodeLine{02958\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_IO\ uint32\_t\ tmpreg;\ \(\backslash\)}}
\DoxyCodeLine{02959\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC\_C1-\/>AHB4ENR,\ RCC\_AHB4ENR\_GPIOGEN);\(\backslash\)}}
\DoxyCodeLine{02960\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ an\ RCC\ peripheral\ clock\ enabling\ */}\textcolor{preprocessor}{\ \(\backslash\)}}
\DoxyCodeLine{02961\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC\_C1-\/>AHB4ENR,\ RCC\_AHB4ENR\_GPIOGEN);\(\backslash\)}}
\DoxyCodeLine{02962\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ UNUSED(tmpreg);\ \(\backslash\)}}
\DoxyCodeLine{02963\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ while(0)}}
\DoxyCodeLine{02964\ }
\DoxyCodeLine{02965\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_GPIOH\_CLK\_ENABLE()\ \ \ do\ \{\ \(\backslash\)}}
\DoxyCodeLine{02966\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_IO\ uint32\_t\ tmpreg;\ \(\backslash\)}}
\DoxyCodeLine{02967\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC\_C1-\/>AHB4ENR,\ RCC\_AHB4ENR\_GPIOHEN);\(\backslash\)}}
\DoxyCodeLine{02968\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ an\ RCC\ peripheral\ clock\ enabling\ */}\textcolor{preprocessor}{\ \(\backslash\)}}
\DoxyCodeLine{02969\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC\_C1-\/>AHB4ENR,\ RCC\_AHB4ENR\_GPIOHEN);\(\backslash\)}}
\DoxyCodeLine{02970\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ UNUSED(tmpreg);\ \(\backslash\)}}
\DoxyCodeLine{02971\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ while(0)}}
\DoxyCodeLine{02972\ }
\DoxyCodeLine{02973\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_GPIOI\_CLK\_ENABLE()\ \ \ do\ \{\ \(\backslash\)}}
\DoxyCodeLine{02974\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_IO\ uint32\_t\ tmpreg;\ \(\backslash\)}}
\DoxyCodeLine{02975\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC\_C1-\/>AHB4ENR,\ RCC\_AHB4ENR\_GPIOIEN);\(\backslash\)}}
\DoxyCodeLine{02976\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ an\ RCC\ peripheral\ clock\ enabling\ */}\textcolor{preprocessor}{\ \(\backslash\)}}
\DoxyCodeLine{02977\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC\_C1-\/>AHB4ENR,\ RCC\_AHB4ENR\_GPIOIEN);\(\backslash\)}}
\DoxyCodeLine{02978\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ UNUSED(tmpreg);\ \(\backslash\)}}
\DoxyCodeLine{02979\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ while(0)}}
\DoxyCodeLine{02980\ }
\DoxyCodeLine{02981\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_GPIOJ\_CLK\_ENABLE()\ \ \ do\ \{\ \(\backslash\)}}
\DoxyCodeLine{02982\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_IO\ uint32\_t\ tmpreg;\ \(\backslash\)}}
\DoxyCodeLine{02983\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC\_C1-\/>AHB4ENR,\ RCC\_AHB4ENR\_GPIOJEN);\(\backslash\)}}
\DoxyCodeLine{02984\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ an\ RCC\ peripheral\ clock\ enabling\ */}\textcolor{preprocessor}{\ \(\backslash\)}}
\DoxyCodeLine{02985\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC\_C1-\/>AHB4ENR,\ RCC\_AHB4ENR\_GPIOJEN);\(\backslash\)}}
\DoxyCodeLine{02986\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ UNUSED(tmpreg);\ \(\backslash\)}}
\DoxyCodeLine{02987\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ while(0)}}
\DoxyCodeLine{02988\ }
\DoxyCodeLine{02989\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_GPIOK\_CLK\_ENABLE()\ \ \ do\ \{\ \(\backslash\)}}
\DoxyCodeLine{02990\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_IO\ uint32\_t\ tmpreg;\ \(\backslash\)}}
\DoxyCodeLine{02991\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC\_C1-\/>AHB4ENR,\ RCC\_AHB4ENR\_GPIOKEN);\(\backslash\)}}
\DoxyCodeLine{02992\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ an\ RCC\ peripheral\ clock\ enabling\ */}\textcolor{preprocessor}{\ \(\backslash\)}}
\DoxyCodeLine{02993\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC\_C1-\/>AHB4ENR,\ RCC\_AHB4ENR\_GPIOKEN);\(\backslash\)}}
\DoxyCodeLine{02994\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ UNUSED(tmpreg);\ \(\backslash\)}}
\DoxyCodeLine{02995\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ while(0)}}
\DoxyCodeLine{02996\ }
\DoxyCodeLine{02997\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_CRC\_CLK\_ENABLE()\ \ \ do\ \{\ \(\backslash\)}}
\DoxyCodeLine{02998\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_IO\ uint32\_t\ tmpreg;\ \(\backslash\)}}
\DoxyCodeLine{02999\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC\_C1-\/>AHB4ENR,\ RCC\_AHB4ENR\_CRCEN);\(\backslash\)}}
\DoxyCodeLine{03000\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ an\ RCC\ peripheral\ clock\ enabling\ */}\textcolor{preprocessor}{\ \(\backslash\)}}
\DoxyCodeLine{03001\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC\_C1-\/>AHB4ENR,\ RCC\_AHB4ENR\_CRCEN);\(\backslash\)}}
\DoxyCodeLine{03002\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ UNUSED(tmpreg);\ \(\backslash\)}}
\DoxyCodeLine{03003\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ while(0)}}
\DoxyCodeLine{03004\ }
\DoxyCodeLine{03005\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_BDMA\_CLK\_ENABLE()\ \ \ do\ \{\ \(\backslash\)}}
\DoxyCodeLine{03006\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_IO\ uint32\_t\ tmpreg;\ \(\backslash\)}}
\DoxyCodeLine{03007\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC\_C1-\/>AHB4ENR,\ RCC\_AHB4ENR\_BDMAEN);\(\backslash\)}}
\DoxyCodeLine{03008\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ an\ RCC\ peripheral\ clock\ enabling\ */}\textcolor{preprocessor}{\ \(\backslash\)}}
\DoxyCodeLine{03009\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC\_C1-\/>AHB4ENR,\ RCC\_AHB4ENR\_BDMAEN);\(\backslash\)}}
\DoxyCodeLine{03010\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ UNUSED(tmpreg);\ \(\backslash\)}}
\DoxyCodeLine{03011\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ while(0)}}
\DoxyCodeLine{03012\ }
\DoxyCodeLine{03013\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_ADC3\_CLK\_ENABLE()\ \ \ do\ \{\ \(\backslash\)}}
\DoxyCodeLine{03014\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_IO\ uint32\_t\ tmpreg;\ \(\backslash\)}}
\DoxyCodeLine{03015\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC\_C1-\/>AHB4ENR,\ RCC\_AHB4ENR\_ADC3EN);\(\backslash\)}}
\DoxyCodeLine{03016\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ an\ RCC\ peripheral\ clock\ enabling\ */}\textcolor{preprocessor}{\ \(\backslash\)}}
\DoxyCodeLine{03017\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC\_C1-\/>AHB4ENR,\ RCC\_AHB4ENR\_ADC3EN);\(\backslash\)}}
\DoxyCodeLine{03018\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ UNUSED(tmpreg);\ \(\backslash\)}}
\DoxyCodeLine{03019\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ while(0)}}
\DoxyCodeLine{03020\ }
\DoxyCodeLine{03021\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_HSEM\_CLK\_ENABLE()\ \ \ do\ \{\ \(\backslash\)}}
\DoxyCodeLine{03022\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_IO\ uint32\_t\ tmpreg;\ \(\backslash\)}}
\DoxyCodeLine{03023\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC\_C1-\/>AHB4ENR,\ RCC\_AHB4ENR\_HSEMEN);\(\backslash\)}}
\DoxyCodeLine{03024\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ an\ RCC\ peripheral\ clock\ enabling\ */}\textcolor{preprocessor}{\ \(\backslash\)}}
\DoxyCodeLine{03025\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC\_C1-\/>AHB4ENR,\ RCC\_AHB4ENR\_HSEMEN);\(\backslash\)}}
\DoxyCodeLine{03026\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ UNUSED(tmpreg);\ \(\backslash\)}}
\DoxyCodeLine{03027\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ while(0)}}
\DoxyCodeLine{03028\ }
\DoxyCodeLine{03029\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_BKPRAM\_CLK\_ENABLE()\ \ \ do\ \{\ \(\backslash\)}}
\DoxyCodeLine{03030\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_IO\ uint32\_t\ tmpreg;\ \(\backslash\)}}
\DoxyCodeLine{03031\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC\_C1-\/>AHB4ENR,\ RCC\_AHB4ENR\_BKPRAMEN);\(\backslash\)}}
\DoxyCodeLine{03032\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ an\ RCC\ peripheral\ clock\ enabling\ */}\textcolor{preprocessor}{\ \(\backslash\)}}
\DoxyCodeLine{03033\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC\_C1-\/>AHB4ENR,\ RCC\_AHB4ENR\_BKPRAMEN);\(\backslash\)}}
\DoxyCodeLine{03034\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ UNUSED(tmpreg);\ \(\backslash\)}}
\DoxyCodeLine{03035\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ while(0)}}
\DoxyCodeLine{03036\ }
\DoxyCodeLine{03037\ }
\DoxyCodeLine{03038\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_GPIOA\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>AHB4ENR)\ \&=\ \string~\ (RCC\_AHB4ENR\_GPIOAEN)}}
\DoxyCodeLine{03039\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_GPIOB\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>AHB4ENR)\ \&=\ \string~\ (RCC\_AHB4ENR\_GPIOBEN)}}
\DoxyCodeLine{03040\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_GPIOC\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>AHB4ENR)\ \&=\ \string~\ (RCC\_AHB4ENR\_GPIOCEN)}}
\DoxyCodeLine{03041\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_GPIOD\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>AHB4ENR)\ \&=\ \string~\ (RCC\_AHB4ENR\_GPIODEN)}}
\DoxyCodeLine{03042\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_GPIOE\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>AHB4ENR)\ \&=\ \string~\ (RCC\_AHB4ENR\_GPIOEEN)}}
\DoxyCodeLine{03043\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_GPIOF\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>AHB4ENR)\ \&=\ \string~\ (RCC\_AHB4ENR\_GPIOFEN)}}
\DoxyCodeLine{03044\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_GPIOG\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>AHB4ENR)\ \&=\ \string~\ (RCC\_AHB4ENR\_GPIOGEN)}}
\DoxyCodeLine{03045\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_GPIOH\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>AHB4ENR)\ \&=\ \string~\ (RCC\_AHB4ENR\_GPIOHEN)}}
\DoxyCodeLine{03046\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_GPIOI\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>AHB4ENR)\ \&=\ \string~\ (RCC\_AHB4ENR\_GPIOIEN)}}
\DoxyCodeLine{03047\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_GPIOJ\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>AHB4ENR)\ \&=\ \string~\ (RCC\_AHB4ENR\_GPIOJEN)}}
\DoxyCodeLine{03048\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_GPIOK\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>AHB4ENR)\ \&=\ \string~\ (RCC\_AHB4ENR\_GPIOKEN)}}
\DoxyCodeLine{03049\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_CRC\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>AHB4ENR)\ \&=\ \string~\ (RCC\_AHB4ENR\_CRCEN)}}
\DoxyCodeLine{03050\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_BDMA\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>AHB4ENR)\ \&=\ \string~\ (RCC\_AHB4ENR\_BDMAEN)}}
\DoxyCodeLine{03051\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_ADC3\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>AHB4ENR)\ \&=\ \string~\ (RCC\_AHB4ENR\_ADC3EN)}}
\DoxyCodeLine{03052\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_HSEM\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>AHB4ENR)\ \&=\ \string~\ (RCC\_AHB4ENR\_HSEMEN)}}
\DoxyCodeLine{03053\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_BKPRAM\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>AHB4ENR)\ \&=\ \string~\ (RCC\_AHB4ENR\_BKPRAMEN)}}
\DoxyCodeLine{03054\ }
\DoxyCodeLine{03055\ }
\DoxyCodeLine{03061\ }
\DoxyCodeLine{03062\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_LTDC\_CLK\_ENABLE()\ \ \ do\ \{\ \(\backslash\)}}
\DoxyCodeLine{03063\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_IO\ uint32\_t\ tmpreg;\ \(\backslash\)}}
\DoxyCodeLine{03064\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC\_C1-\/>APB3ENR,\ RCC\_APB3ENR\_LTDCEN);\(\backslash\)}}
\DoxyCodeLine{03065\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ an\ RCC\ peripheral\ clock\ enabling\ */}\textcolor{preprocessor}{\ \(\backslash\)}}
\DoxyCodeLine{03066\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC\_C1-\/>APB3ENR,\ RCC\_APB3ENR\_LTDCEN);\(\backslash\)}}
\DoxyCodeLine{03067\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ UNUSED(tmpreg);\ \(\backslash\)}}
\DoxyCodeLine{03068\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ while(0)}}
\DoxyCodeLine{03069\ }
\DoxyCodeLine{03070\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_DSI\_CLK\_ENABLE()\ \ \ do\ \{\ \(\backslash\)}}
\DoxyCodeLine{03071\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_IO\ uint32\_t\ tmpreg;\ \(\backslash\)}}
\DoxyCodeLine{03072\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC\_C1-\/>APB3ENR,\ RCC\_APB3ENR\_DSIEN);\(\backslash\)}}
\DoxyCodeLine{03073\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ an\ RCC\ peripheral\ clock\ enabling\ */}\textcolor{preprocessor}{\ \(\backslash\)}}
\DoxyCodeLine{03074\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC\_C1-\/>APB3ENR,\ RCC\_APB3ENR\_DSIEN);\(\backslash\)}}
\DoxyCodeLine{03075\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ UNUSED(tmpreg);\ \(\backslash\)}}
\DoxyCodeLine{03076\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ while(0)}}
\DoxyCodeLine{03077\ }
\DoxyCodeLine{03078\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_WWDG1\_CLK\_ENABLE()\ \ \ do\ \{\ \(\backslash\)}}
\DoxyCodeLine{03079\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_IO\ uint32\_t\ tmpreg;\ \(\backslash\)}}
\DoxyCodeLine{03080\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC\_C1-\/>APB3ENR,\ RCC\_APB3ENR\_WWDG1EN);\(\backslash\)}}
\DoxyCodeLine{03081\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ an\ RCC\ peripheral\ clock\ enabling\ */}\textcolor{preprocessor}{\ \(\backslash\)}}
\DoxyCodeLine{03082\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC\_C1-\/>APB3ENR,\ RCC\_APB3ENR\_WWDG1EN);\(\backslash\)}}
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\DoxyCodeLine{03085\ }
\DoxyCodeLine{03086\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_LTDC\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB3ENR)\ \&=\ \string~\ (RCC\_APB3ENR\_LTDCEN)}}
\DoxyCodeLine{03087\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_DSI\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB3ENR)\ \&=\ \string~\ (RCC\_APB3ENR\_DSIEN)}}
\DoxyCodeLine{03088\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_WWDG1\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB3ENR)\ \&=\ \string~\ (RCC\_APB3ENR\_WWDG1EN)}}
\DoxyCodeLine{03089\ }
\DoxyCodeLine{03095\ }
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\DoxyCodeLine{03103\ }
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\DoxyCodeLine{03105\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_IO\ uint32\_t\ tmpreg;\ \(\backslash\)}}
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\DoxyCodeLine{03111\ }
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\DoxyCodeLine{03119\ }
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\DoxyCodeLine{03127\ }
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\DoxyCodeLine{03135\ }
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\DoxyCodeLine{03143\ }
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\DoxyCodeLine{03151\ }
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\DoxyCodeLine{03159\ }
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\DoxyCodeLine{03167\ }
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\DoxyCodeLine{03175\ }
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\DoxyCodeLine{03204\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC\_C1-\/>APB1LENR,\ RCC\_APB1LENR\_SPDIFRXEN);\(\backslash\)}}
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\DoxyCodeLine{03207\ }
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\DoxyCodeLine{03215\ }
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\DoxyCodeLine{03223\ }
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\DoxyCodeLine{03231\ }
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\DoxyCodeLine{03239\ }
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\DoxyCodeLine{03247\ }
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\DoxyCodeLine{03255\ }
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\DoxyCodeLine{03263\ }
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\DoxyCodeLine{03271\ }
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\DoxyCodeLine{03303\ }
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\DoxyCodeLine{03311\ }
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\DoxyCodeLine{03319\ }
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\DoxyCodeLine{03322\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC\_C1-\/>APB1HENR,\ RCC\_APB1HENR\_MDIOSEN);\(\backslash\)}}
\DoxyCodeLine{03323\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ an\ RCC\ peripheral\ clock\ enabling\ */}\textcolor{preprocessor}{\ \(\backslash\)}}
\DoxyCodeLine{03324\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC\_C1-\/>APB1HENR,\ RCC\_APB1HENR\_MDIOSEN);\(\backslash\)}}
\DoxyCodeLine{03325\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ UNUSED(tmpreg);\ \(\backslash\)}}
\DoxyCodeLine{03326\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ while(0)}}
\DoxyCodeLine{03327\ }
\DoxyCodeLine{03328\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_FDCAN\_CLK\_ENABLE()\ \ \ do\ \{\ \(\backslash\)}}
\DoxyCodeLine{03329\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_IO\ uint32\_t\ tmpreg;\ \(\backslash\)}}
\DoxyCodeLine{03330\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC\_C1-\/>APB1HENR,\ RCC\_APB1HENR\_FDCANEN);\(\backslash\)}}
\DoxyCodeLine{03331\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ an\ RCC\ peripheral\ clock\ enabling\ */}\textcolor{preprocessor}{\ \(\backslash\)}}
\DoxyCodeLine{03332\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC\_C1-\/>APB1HENR,\ RCC\_APB1HENR\_FDCANEN);\(\backslash\)}}
\DoxyCodeLine{03333\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ UNUSED(tmpreg);\ \(\backslash\)}}
\DoxyCodeLine{03334\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ while(0)}}
\DoxyCodeLine{03335\ }
\DoxyCodeLine{03336\ }
\DoxyCodeLine{03337\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_TIM2\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB1LENR)\ \&=\ \string~\ (RCC\_APB1LENR\_TIM2EN)}}
\DoxyCodeLine{03338\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_TIM3\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB1LENR)\ \&=\ \string~\ (RCC\_APB1LENR\_TIM3EN)}}
\DoxyCodeLine{03339\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_TIM4\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB1LENR)\ \&=\ \string~\ (RCC\_APB1LENR\_TIM4EN)}}
\DoxyCodeLine{03340\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_TIM5\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB1LENR)\ \&=\ \string~\ (RCC\_APB1LENR\_TIM5EN)}}
\DoxyCodeLine{03341\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_TIM6\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB1LENR)\ \&=\ \string~\ (RCC\_APB1LENR\_TIM6EN)}}
\DoxyCodeLine{03342\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_TIM7\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB1LENR)\ \&=\ \string~\ (RCC\_APB1LENR\_TIM7EN)}}
\DoxyCodeLine{03343\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_TIM12\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB1LENR)\ \&=\ \string~\ (RCC\_APB1LENR\_TIM12EN)}}
\DoxyCodeLine{03344\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_TIM13\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB1LENR)\ \&=\ \string~\ (RCC\_APB1LENR\_TIM13EN)}}
\DoxyCodeLine{03345\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_TIM14\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB1LENR)\ \&=\ \string~\ (RCC\_APB1LENR\_TIM14EN)}}
\DoxyCodeLine{03346\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_LPTIM1\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB1LENR)\ \&=\ \string~\ (RCC\_APB1LENR\_LPTIM1EN)}}
\DoxyCodeLine{03347\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_WWDG2\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB1LENR)\ \&=\ \string~\ (RCC\_APB1LENR\_WWDG2EN)}}
\DoxyCodeLine{03348\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_SPI2\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB1LENR)\ \&=\ \string~\ (RCC\_APB1LENR\_SPI2EN)}}
\DoxyCodeLine{03349\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_SPI3\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB1LENR)\ \&=\ \string~\ (RCC\_APB1LENR\_SPI3EN)}}
\DoxyCodeLine{03350\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_SPDIFRX\_CLK\_DISABLE()\ \ \ \ \ \ \ \ (RCC\_C1-\/>APB1LENR)\ \&=\ \string~\ (RCC\_APB1LENR\_SPDIFRXEN)}}
\DoxyCodeLine{03351\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_USART2\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB1LENR)\ \&=\ \string~\ (RCC\_APB1LENR\_USART2EN)}}
\DoxyCodeLine{03352\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_USART3\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB1LENR)\ \&=\ \string~\ (RCC\_APB1LENR\_USART3EN)}}
\DoxyCodeLine{03353\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_UART4\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB1LENR)\ \&=\ \string~\ (RCC\_APB1LENR\_UART4EN)}}
\DoxyCodeLine{03354\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_UART5\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB1LENR)\ \&=\ \string~\ (RCC\_APB1LENR\_UART5EN)}}
\DoxyCodeLine{03355\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_I2C1\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB1LENR)\ \&=\ \string~\ (RCC\_APB1LENR\_I2C1EN)}}
\DoxyCodeLine{03356\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_I2C2\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB1LENR)\ \&=\ \string~\ (RCC\_APB1LENR\_I2C2EN)}}
\DoxyCodeLine{03357\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_I2C3\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB1LENR)\ \&=\ \string~\ (RCC\_APB1LENR\_I2C3EN)}}
\DoxyCodeLine{03358\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_CEC\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB1LENR)\ \&=\ \string~\ (RCC\_APB1LENR\_CECEN)}}
\DoxyCodeLine{03359\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_DAC12\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB1LENR)\ \&=\ \string~\ (RCC\_APB1LENR\_DAC12EN)}}
\DoxyCodeLine{03360\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_UART7\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB1LENR)\ \&=\ \string~\ (RCC\_APB1LENR\_UART7EN)}}
\DoxyCodeLine{03361\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_UART8\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB1LENR)\ \&=\ \string~\ (RCC\_APB1LENR\_UART8EN)}}
\DoxyCodeLine{03362\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_CRS\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB1HENR)\ \&=\ \string~\ (RCC\_APB1HENR\_CRSEN)}}
\DoxyCodeLine{03363\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_SWPMI\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB1HENR)\ \&=\ \string~\ (RCC\_APB1HENR\_SWPMIEN)}}
\DoxyCodeLine{03364\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_OPAMP\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB1HENR)\ \&=\ \string~\ (RCC\_APB1HENR\_OPAMPEN)}}
\DoxyCodeLine{03365\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_MDIOS\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB1HENR)\ \&=\ \string~\ (RCC\_APB1HENR\_MDIOSEN)}}
\DoxyCodeLine{03366\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_FDCAN\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB1HENR)\ \&=\ \string~\ (RCC\_APB1HENR\_FDCANEN)}}
\DoxyCodeLine{03367\ }
\DoxyCodeLine{03373\ }
\DoxyCodeLine{03374\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_TIM1\_CLK\_ENABLE()\ \ \ do\ \{\ \(\backslash\)}}
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\DoxyCodeLine{03376\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC\_C1-\/>APB2ENR,\ RCC\_APB2ENR\_TIM1EN);\(\backslash\)}}
\DoxyCodeLine{03377\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ an\ RCC\ peripheral\ clock\ enabling\ */}\textcolor{preprocessor}{\ \(\backslash\)}}
\DoxyCodeLine{03378\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC\_C1-\/>APB2ENR,\ RCC\_APB2ENR\_TIM1EN);\(\backslash\)}}
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\DoxyCodeLine{03380\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ while(0)}}
\DoxyCodeLine{03381\ }
\DoxyCodeLine{03382\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_TIM8\_CLK\_ENABLE()\ \ \ do\ \{\ \(\backslash\)}}
\DoxyCodeLine{03383\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_IO\ uint32\_t\ tmpreg;\ \(\backslash\)}}
\DoxyCodeLine{03384\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC\_C1-\/>APB2ENR,\ RCC\_APB2ENR\_TIM8EN);\(\backslash\)}}
\DoxyCodeLine{03385\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ an\ RCC\ peripheral\ clock\ enabling\ */}\textcolor{preprocessor}{\ \(\backslash\)}}
\DoxyCodeLine{03386\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC\_C1-\/>APB2ENR,\ RCC\_APB2ENR\_TIM8EN);\(\backslash\)}}
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\DoxyCodeLine{03388\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ while(0)}}
\DoxyCodeLine{03389\ }
\DoxyCodeLine{03390\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_USART1\_CLK\_ENABLE()\ \ \ do\ \{\ \(\backslash\)}}
\DoxyCodeLine{03391\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_IO\ uint32\_t\ tmpreg;\ \(\backslash\)}}
\DoxyCodeLine{03392\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC\_C1-\/>APB2ENR,\ RCC\_APB2ENR\_USART1EN);\(\backslash\)}}
\DoxyCodeLine{03393\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ an\ RCC\ peripheral\ clock\ enabling\ */}\textcolor{preprocessor}{\ \(\backslash\)}}
\DoxyCodeLine{03394\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC\_C1-\/>APB2ENR,\ RCC\_APB2ENR\_USART1EN);\(\backslash\)}}
\DoxyCodeLine{03395\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ UNUSED(tmpreg);\ \(\backslash\)}}
\DoxyCodeLine{03396\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ while(0)}}
\DoxyCodeLine{03397\ }
\DoxyCodeLine{03398\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_USART6\_CLK\_ENABLE()\ \ \ do\ \{\ \(\backslash\)}}
\DoxyCodeLine{03399\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_IO\ uint32\_t\ tmpreg;\ \(\backslash\)}}
\DoxyCodeLine{03400\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC\_C1-\/>APB2ENR,\ RCC\_APB2ENR\_USART6EN);\(\backslash\)}}
\DoxyCodeLine{03401\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ an\ RCC\ peripheral\ clock\ enabling\ */}\textcolor{preprocessor}{\ \(\backslash\)}}
\DoxyCodeLine{03402\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC\_C1-\/>APB2ENR,\ RCC\_APB2ENR\_USART6EN);\(\backslash\)}}
\DoxyCodeLine{03403\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ UNUSED(tmpreg);\ \(\backslash\)}}
\DoxyCodeLine{03404\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ while(0)}}
\DoxyCodeLine{03405\ }
\DoxyCodeLine{03406\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_SPI1\_CLK\_ENABLE()\ \ \ do\ \{\ \(\backslash\)}}
\DoxyCodeLine{03407\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_IO\ uint32\_t\ tmpreg;\ \(\backslash\)}}
\DoxyCodeLine{03408\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC\_C1-\/>APB2ENR,\ RCC\_APB2ENR\_SPI1EN);\(\backslash\)}}
\DoxyCodeLine{03409\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ an\ RCC\ peripheral\ clock\ enabling\ */}\textcolor{preprocessor}{\ \(\backslash\)}}
\DoxyCodeLine{03410\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC\_C1-\/>APB2ENR,\ RCC\_APB2ENR\_SPI1EN);\(\backslash\)}}
\DoxyCodeLine{03411\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ UNUSED(tmpreg);\ \(\backslash\)}}
\DoxyCodeLine{03412\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ while(0)}}
\DoxyCodeLine{03413\ }
\DoxyCodeLine{03414\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_SPI4\_CLK\_ENABLE()\ \ \ do\ \{\ \(\backslash\)}}
\DoxyCodeLine{03415\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_IO\ uint32\_t\ tmpreg;\ \(\backslash\)}}
\DoxyCodeLine{03416\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC\_C1-\/>APB2ENR,\ RCC\_APB2ENR\_SPI4EN);\(\backslash\)}}
\DoxyCodeLine{03417\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ an\ RCC\ peripheral\ clock\ enabling\ */}\textcolor{preprocessor}{\ \(\backslash\)}}
\DoxyCodeLine{03418\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC\_C1-\/>APB2ENR,\ RCC\_APB2ENR\_SPI4EN);\(\backslash\)}}
\DoxyCodeLine{03419\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ UNUSED(tmpreg);\ \(\backslash\)}}
\DoxyCodeLine{03420\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ while(0)}}
\DoxyCodeLine{03421\ }
\DoxyCodeLine{03422\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_TIM15\_CLK\_ENABLE()\ \ \ do\ \{\ \(\backslash\)}}
\DoxyCodeLine{03423\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_IO\ uint32\_t\ tmpreg;\ \(\backslash\)}}
\DoxyCodeLine{03424\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC\_C1-\/>APB2ENR,\ RCC\_APB2ENR\_TIM15EN);\(\backslash\)}}
\DoxyCodeLine{03425\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ an\ RCC\ peripheral\ clock\ enabling\ */}\textcolor{preprocessor}{\ \(\backslash\)}}
\DoxyCodeLine{03426\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC\_C1-\/>APB2ENR,\ RCC\_APB2ENR\_TIM15EN);\(\backslash\)}}
\DoxyCodeLine{03427\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ UNUSED(tmpreg);\ \(\backslash\)}}
\DoxyCodeLine{03428\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ while(0)}}
\DoxyCodeLine{03429\ }
\DoxyCodeLine{03430\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_TIM16\_CLK\_ENABLE()\ \ \ do\ \{\ \(\backslash\)}}
\DoxyCodeLine{03431\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_IO\ uint32\_t\ tmpreg;\ \(\backslash\)}}
\DoxyCodeLine{03432\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC\_C1-\/>APB2ENR,\ RCC\_APB2ENR\_TIM16EN);\(\backslash\)}}
\DoxyCodeLine{03433\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ an\ RCC\ peripheral\ clock\ enabling\ */}\textcolor{preprocessor}{\ \(\backslash\)}}
\DoxyCodeLine{03434\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC\_C1-\/>APB2ENR,\ RCC\_APB2ENR\_TIM16EN);\(\backslash\)}}
\DoxyCodeLine{03435\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ UNUSED(tmpreg);\ \(\backslash\)}}
\DoxyCodeLine{03436\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ while(0)}}
\DoxyCodeLine{03437\ }
\DoxyCodeLine{03438\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_TIM17\_CLK\_ENABLE()\ \ \ do\ \{\ \(\backslash\)}}
\DoxyCodeLine{03439\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_IO\ uint32\_t\ tmpreg;\ \(\backslash\)}}
\DoxyCodeLine{03440\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC\_C1-\/>APB2ENR,\ RCC\_APB2ENR\_TIM17EN);\(\backslash\)}}
\DoxyCodeLine{03441\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ an\ RCC\ peripheral\ clock\ enabling\ */}\textcolor{preprocessor}{\ \(\backslash\)}}
\DoxyCodeLine{03442\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC\_C1-\/>APB2ENR,\ RCC\_APB2ENR\_TIM17EN);\(\backslash\)}}
\DoxyCodeLine{03443\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ UNUSED(tmpreg);\ \(\backslash\)}}
\DoxyCodeLine{03444\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ while(0)}}
\DoxyCodeLine{03445\ }
\DoxyCodeLine{03446\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_SPI5\_CLK\_ENABLE()\ \ \ do\ \{\ \(\backslash\)}}
\DoxyCodeLine{03447\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_IO\ uint32\_t\ tmpreg;\ \(\backslash\)}}
\DoxyCodeLine{03448\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC\_C1-\/>APB2ENR,\ RCC\_APB2ENR\_SPI5EN);\(\backslash\)}}
\DoxyCodeLine{03449\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ an\ RCC\ peripheral\ clock\ enabling\ */}\textcolor{preprocessor}{\ \(\backslash\)}}
\DoxyCodeLine{03450\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC\_C1-\/>APB2ENR,\ RCC\_APB2ENR\_SPI5EN);\(\backslash\)}}
\DoxyCodeLine{03451\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ UNUSED(tmpreg);\ \(\backslash\)}}
\DoxyCodeLine{03452\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ while(0)}}
\DoxyCodeLine{03453\ }
\DoxyCodeLine{03454\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_SAI1\_CLK\_ENABLE()\ \ \ do\ \{\ \(\backslash\)}}
\DoxyCodeLine{03455\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_IO\ uint32\_t\ tmpreg;\ \(\backslash\)}}
\DoxyCodeLine{03456\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC\_C1-\/>APB2ENR,\ RCC\_APB2ENR\_SAI1EN);\(\backslash\)}}
\DoxyCodeLine{03457\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ an\ RCC\ peripheral\ clock\ enabling\ */}\textcolor{preprocessor}{\ \(\backslash\)}}
\DoxyCodeLine{03458\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC\_C1-\/>APB2ENR,\ RCC\_APB2ENR\_SAI1EN);\(\backslash\)}}
\DoxyCodeLine{03459\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ UNUSED(tmpreg);\ \(\backslash\)}}
\DoxyCodeLine{03460\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ while(0)}}
\DoxyCodeLine{03461\ }
\DoxyCodeLine{03462\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_SAI2\_CLK\_ENABLE()\ \ \ do\ \{\ \(\backslash\)}}
\DoxyCodeLine{03463\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_IO\ uint32\_t\ tmpreg;\ \(\backslash\)}}
\DoxyCodeLine{03464\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC\_C1-\/>APB2ENR,\ RCC\_APB2ENR\_SAI2EN);\(\backslash\)}}
\DoxyCodeLine{03465\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ an\ RCC\ peripheral\ clock\ enabling\ */}\textcolor{preprocessor}{\ \(\backslash\)}}
\DoxyCodeLine{03466\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC\_C1-\/>APB2ENR,\ RCC\_APB2ENR\_SAI2EN);\(\backslash\)}}
\DoxyCodeLine{03467\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ UNUSED(tmpreg);\ \(\backslash\)}}
\DoxyCodeLine{03468\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ while(0)}}
\DoxyCodeLine{03469\ }
\DoxyCodeLine{03470\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_SAI3\_CLK\_ENABLE()\ \ \ do\ \{\ \(\backslash\)}}
\DoxyCodeLine{03471\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_IO\ uint32\_t\ tmpreg;\ \(\backslash\)}}
\DoxyCodeLine{03472\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC\_C1-\/>APB2ENR,\ RCC\_APB2ENR\_SAI3EN);\(\backslash\)}}
\DoxyCodeLine{03473\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ an\ RCC\ peripheral\ clock\ enabling\ */}\textcolor{preprocessor}{\ \(\backslash\)}}
\DoxyCodeLine{03474\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC\_C1-\/>APB2ENR,\ RCC\_APB2ENR\_SAI3EN);\(\backslash\)}}
\DoxyCodeLine{03475\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ UNUSED(tmpreg);\ \(\backslash\)}}
\DoxyCodeLine{03476\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ while(0)}}
\DoxyCodeLine{03477\ }
\DoxyCodeLine{03478\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_DFSDM1\_CLK\_ENABLE()\ \ \ do\ \{\ \(\backslash\)}}
\DoxyCodeLine{03479\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_IO\ uint32\_t\ tmpreg;\ \(\backslash\)}}
\DoxyCodeLine{03480\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC\_C1-\/>APB2ENR,\ RCC\_APB2ENR\_DFSDM1EN);\(\backslash\)}}
\DoxyCodeLine{03481\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ an\ RCC\ peripheral\ clock\ enabling\ */}\textcolor{preprocessor}{\ \(\backslash\)}}
\DoxyCodeLine{03482\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC\_C1-\/>APB2ENR,\ RCC\_APB2ENR\_DFSDM1EN);\(\backslash\)}}
\DoxyCodeLine{03483\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ UNUSED(tmpreg);\ \(\backslash\)}}
\DoxyCodeLine{03484\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ while(0)}}
\DoxyCodeLine{03485\ }
\DoxyCodeLine{03486\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_HRTIM1\_CLK\_ENABLE()\ \ \ do\ \{\ \(\backslash\)}}
\DoxyCodeLine{03487\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_IO\ uint32\_t\ tmpreg;\ \(\backslash\)}}
\DoxyCodeLine{03488\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC\_C1-\/>APB2ENR,\ RCC\_APB2ENR\_HRTIMEN);\(\backslash\)}}
\DoxyCodeLine{03489\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ an\ RCC\ peripheral\ clock\ enabling\ */}\textcolor{preprocessor}{\ \(\backslash\)}}
\DoxyCodeLine{03490\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC\_C1-\/>APB2ENR,\ RCC\_APB2ENR\_HRTIMEN);\(\backslash\)}}
\DoxyCodeLine{03491\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ UNUSED(tmpreg);\ \(\backslash\)}}
\DoxyCodeLine{03492\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ while(0)}}
\DoxyCodeLine{03493\ }
\DoxyCodeLine{03494\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_TIM1\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB2ENR)\ \&=\ \string~\ (RCC\_APB2ENR\_TIM1EN)}}
\DoxyCodeLine{03495\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_TIM8\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB2ENR)\ \&=\ \string~\ (RCC\_APB2ENR\_TIM8EN)}}
\DoxyCodeLine{03496\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_USART1\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB2ENR)\ \&=\ \string~\ (RCC\_APB2ENR\_USART1EN)}}
\DoxyCodeLine{03497\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_USART6\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB2ENR)\ \&=\ \string~\ (RCC\_APB2ENR\_USART6EN)}}
\DoxyCodeLine{03498\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_SPI1\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB2ENR)\ \&=\ \string~\ (RCC\_APB2ENR\_SPI1EN)}}
\DoxyCodeLine{03499\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_SPI4\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB2ENR)\ \&=\ \string~\ (RCC\_APB2ENR\_SPI4EN)}}
\DoxyCodeLine{03500\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_TIM15\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB2ENR)\ \&=\ \string~\ (RCC\_APB2ENR\_TIM15EN)}}
\DoxyCodeLine{03501\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_TIM16\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB2ENR)\ \&=\ \string~\ (RCC\_APB2ENR\_TIM16EN)}}
\DoxyCodeLine{03502\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_TIM17\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB2ENR)\ \&=\ \string~\ (RCC\_APB2ENR\_TIM17EN)}}
\DoxyCodeLine{03503\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_SPI5\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB2ENR)\ \&=\ \string~\ (RCC\_APB2ENR\_SPI5EN)}}
\DoxyCodeLine{03504\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_SAI1\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB2ENR)\ \&=\ \string~\ (RCC\_APB2ENR\_SAI1EN)}}
\DoxyCodeLine{03505\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_SAI2\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB2ENR)\ \&=\ \string~\ (RCC\_APB2ENR\_SAI2EN)}}
\DoxyCodeLine{03506\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_SAI3\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB2ENR)\ \&=\ \string~\ (RCC\_APB2ENR\_SAI3EN)}}
\DoxyCodeLine{03507\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_DFSDM1\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB2ENR)\ \&=\ \string~\ (RCC\_APB2ENR\_DFSDM1EN)}}
\DoxyCodeLine{03508\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_HRTIM1\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB2ENR)\ \&=\ \string~\ (RCC\_APB2ENR\_HRTIMEN)}}
\DoxyCodeLine{03509\ }
\DoxyCodeLine{03515\ }
\DoxyCodeLine{03516\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_SYSCFG\_CLK\_ENABLE()\ \ \ do\ \{\ \(\backslash\)}}
\DoxyCodeLine{03517\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_IO\ uint32\_t\ tmpreg;\ \(\backslash\)}}
\DoxyCodeLine{03518\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC\_C1-\/>APB4ENR,\ RCC\_APB4ENR\_SYSCFGEN);\(\backslash\)}}
\DoxyCodeLine{03519\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ an\ RCC\ peripheral\ clock\ enabling\ */}\textcolor{preprocessor}{\ \(\backslash\)}}
\DoxyCodeLine{03520\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC\_C1-\/>APB4ENR,\ RCC\_APB4ENR\_SYSCFGEN);\(\backslash\)}}
\DoxyCodeLine{03521\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ UNUSED(tmpreg);\ \(\backslash\)}}
\DoxyCodeLine{03522\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ while(0)}}
\DoxyCodeLine{03523\ }
\DoxyCodeLine{03524\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_LPUART1\_CLK\_ENABLE()\ \ \ do\ \{\ \(\backslash\)}}
\DoxyCodeLine{03525\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_IO\ uint32\_t\ tmpreg;\ \(\backslash\)}}
\DoxyCodeLine{03526\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC\_C1-\/>APB4ENR,\ RCC\_APB4ENR\_LPUART1EN);\(\backslash\)}}
\DoxyCodeLine{03527\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ an\ RCC\ peripheral\ clock\ enabling\ */}\textcolor{preprocessor}{\ \(\backslash\)}}
\DoxyCodeLine{03528\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC\_C1-\/>APB4ENR,\ RCC\_APB4ENR\_LPUART1EN);\(\backslash\)}}
\DoxyCodeLine{03529\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ UNUSED(tmpreg);\ \(\backslash\)}}
\DoxyCodeLine{03530\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ while(0)}}
\DoxyCodeLine{03531\ }
\DoxyCodeLine{03532\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_SPI6\_CLK\_ENABLE()\ \ \ do\ \{\ \(\backslash\)}}
\DoxyCodeLine{03533\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_IO\ uint32\_t\ tmpreg;\ \(\backslash\)}}
\DoxyCodeLine{03534\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC\_C1-\/>APB4ENR,\ RCC\_APB4ENR\_SPI6EN);\(\backslash\)}}
\DoxyCodeLine{03535\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ an\ RCC\ peripheral\ clock\ enabling\ */}\textcolor{preprocessor}{\ \(\backslash\)}}
\DoxyCodeLine{03536\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC\_C1-\/>APB4ENR,\ RCC\_APB4ENR\_SPI6EN);\(\backslash\)}}
\DoxyCodeLine{03537\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ UNUSED(tmpreg);\ \(\backslash\)}}
\DoxyCodeLine{03538\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ while(0)}}
\DoxyCodeLine{03539\ }
\DoxyCodeLine{03540\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_I2C4\_CLK\_ENABLE()\ \ \ do\ \{\ \(\backslash\)}}
\DoxyCodeLine{03541\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_IO\ uint32\_t\ tmpreg;\ \(\backslash\)}}
\DoxyCodeLine{03542\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC\_C1-\/>APB4ENR,\ RCC\_APB4ENR\_I2C4EN);\(\backslash\)}}
\DoxyCodeLine{03543\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ an\ RCC\ peripheral\ clock\ enabling\ */}\textcolor{preprocessor}{\ \(\backslash\)}}
\DoxyCodeLine{03544\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC\_C1-\/>APB4ENR,\ RCC\_APB4ENR\_I2C4EN);\(\backslash\)}}
\DoxyCodeLine{03545\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ UNUSED(tmpreg);\ \(\backslash\)}}
\DoxyCodeLine{03546\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ while(0)}}
\DoxyCodeLine{03547\ }
\DoxyCodeLine{03548\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_LPTIM2\_CLK\_ENABLE()\ \ \ do\ \{\ \(\backslash\)}}
\DoxyCodeLine{03549\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_IO\ uint32\_t\ tmpreg;\ \(\backslash\)}}
\DoxyCodeLine{03550\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC\_C1-\/>APB4ENR,\ RCC\_APB4ENR\_LPTIM2EN);\(\backslash\)}}
\DoxyCodeLine{03551\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ an\ RCC\ peripheral\ clock\ enabling\ */}\textcolor{preprocessor}{\ \(\backslash\)}}
\DoxyCodeLine{03552\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC\_C1-\/>APB4ENR,\ RCC\_APB4ENR\_LPTIM2EN);\(\backslash\)}}
\DoxyCodeLine{03553\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ UNUSED(tmpreg);\ \(\backslash\)}}
\DoxyCodeLine{03554\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ while(0)}}
\DoxyCodeLine{03555\ }
\DoxyCodeLine{03556\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_LPTIM3\_CLK\_ENABLE()\ \ \ do\ \{\ \(\backslash\)}}
\DoxyCodeLine{03557\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_IO\ uint32\_t\ tmpreg;\ \(\backslash\)}}
\DoxyCodeLine{03558\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC\_C1-\/>APB4ENR,\ RCC\_APB4ENR\_LPTIM3EN);\(\backslash\)}}
\DoxyCodeLine{03559\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ an\ RCC\ peripheral\ clock\ enabling\ */}\textcolor{preprocessor}{\ \(\backslash\)}}
\DoxyCodeLine{03560\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC\_C1-\/>APB4ENR,\ RCC\_APB4ENR\_LPTIM3EN);\(\backslash\)}}
\DoxyCodeLine{03561\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ UNUSED(tmpreg);\ \(\backslash\)}}
\DoxyCodeLine{03562\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ while(0)}}
\DoxyCodeLine{03563\ }
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\DoxyCodeLine{03567\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ an\ RCC\ peripheral\ clock\ enabling\ */}\textcolor{preprocessor}{\ \(\backslash\)}}
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\DoxyCodeLine{03571\ }
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\DoxyCodeLine{03574\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC\_C1-\/>APB4ENR,\ RCC\_APB4ENR\_LPTIM5EN);\(\backslash\)}}
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\DoxyCodeLine{03579\ }
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\DoxyCodeLine{03582\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC\_C1-\/>APB4ENR,\ RCC\_APB4ENR\_COMP12EN);\(\backslash\)}}
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\DoxyCodeLine{03585\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ UNUSED(tmpreg);\ \(\backslash\)}}
\DoxyCodeLine{03586\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ while(0)}}
\DoxyCodeLine{03587\ }
\DoxyCodeLine{03588\ }
\DoxyCodeLine{03589\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_VREF\_CLK\_ENABLE()\ \ \ do\ \{\ \(\backslash\)}}
\DoxyCodeLine{03590\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_IO\ uint32\_t\ tmpreg;\ \(\backslash\)}}
\DoxyCodeLine{03591\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC\_C1-\/>APB4ENR,\ RCC\_APB4ENR\_VREFEN);\(\backslash\)}}
\DoxyCodeLine{03592\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ an\ RCC\ peripheral\ clock\ enabling\ */}\textcolor{preprocessor}{\ \(\backslash\)}}
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\DoxyCodeLine{03594\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ UNUSED(tmpreg);\ \(\backslash\)}}
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\DoxyCodeLine{03596\ }
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\DoxyCodeLine{03598\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_IO\ uint32\_t\ tmpreg;\ \(\backslash\)}}
\DoxyCodeLine{03599\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC\_C1-\/>APB4ENR,\ RCC\_APB4ENR\_RTCAPBEN);\(\backslash\)}}
\DoxyCodeLine{03600\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ an\ RCC\ peripheral\ clock\ enabling\ */}\textcolor{preprocessor}{\ \(\backslash\)}}
\DoxyCodeLine{03601\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC\_C1-\/>APB4ENR,\ RCC\_APB4ENR\_RTCAPBEN);\(\backslash\)}}
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\DoxyCodeLine{03603\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ while(0)}}
\DoxyCodeLine{03604\ }
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\DoxyCodeLine{03607\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC\_C1-\/>APB4ENR,\ RCC\_APB4ENR\_SAI4EN);\(\backslash\)}}
\DoxyCodeLine{03608\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ an\ RCC\ peripheral\ clock\ enabling\ */}\textcolor{preprocessor}{\ \(\backslash\)}}
\DoxyCodeLine{03609\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC\_C1-\/>APB4ENR,\ RCC\_APB4ENR\_SAI4EN);\(\backslash\)}}
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\DoxyCodeLine{03612\ }
\DoxyCodeLine{03613\ }
\DoxyCodeLine{03614\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_SYSCFG\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB4ENR)\ \&=\ \string~\ (RCC\_APB4ENR\_SYSCFGEN)}}
\DoxyCodeLine{03615\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_LPUART1\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB4ENR)\ \&=\ \string~\ (RCC\_APB4ENR\_LPUART1EN)}}
\DoxyCodeLine{03616\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_SPI6\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB4ENR)\ \&=\ \string~\ (RCC\_APB4ENR\_SPI6EN)}}
\DoxyCodeLine{03617\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_I2C4\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB4ENR)\ \&=\ \string~\ (RCC\_APB4ENR\_I2C4EN)}}
\DoxyCodeLine{03618\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_LPTIM2\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB4ENR)\ \&=\ \string~\ (RCC\_APB4ENR\_LPTIM2EN)}}
\DoxyCodeLine{03619\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_LPTIM3\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB4ENR)\ \&=\ \string~\ (RCC\_APB4ENR\_LPTIM3EN)}}
\DoxyCodeLine{03620\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_LPTIM4\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB4ENR)\ \&=\ \string~\ (RCC\_APB4ENR\_LPTIM4EN)}}
\DoxyCodeLine{03621\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_LPTIM5\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB4ENR)\ \&=\ \string~\ (RCC\_APB4ENR\_LPTIM5EN)}}
\DoxyCodeLine{03622\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_COMP12\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB4ENR)\ \&=\ \string~\ (RCC\_APB4ENR\_COMP12EN)}}
\DoxyCodeLine{03623\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_VREF\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB4ENR)\ \&=\ \string~\ (RCC\_APB4ENR\_VREFEN)}}
\DoxyCodeLine{03624\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_RTC\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB4ENR)\ \&=\ \string~\ (RCC\_APB4ENR\_RTCAPBEN)}}
\DoxyCodeLine{03625\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_SAI4\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB4ENR)\ \&=\ \string~\ (RCC\_APB4ENR\_SAI4EN)}}
\DoxyCodeLine{03626\ }
\DoxyCodeLine{03627\ \textcolor{comment}{/*\ Exported\ macros\ for\ RCC\_C2\ -\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/*/}}
\DoxyCodeLine{03628\ }
\DoxyCodeLine{03634\ }
\DoxyCodeLine{03635\ }
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\DoxyCodeLine{03638\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC\_C2-\/>AHB3ENR,\ RCC\_AHB3ENR\_MDMAEN);\(\backslash\)}}
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\DoxyCodeLine{03640\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC\_C2-\/>AHB3ENR,\ RCC\_AHB3ENR\_MDMAEN);\(\backslash\)}}
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\DoxyCodeLine{03642\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ while(0)}}
\DoxyCodeLine{03643\ }
\DoxyCodeLine{03644\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_DMA2D\_CLK\_ENABLE()\ \ \ do\ \{\ \(\backslash\)}}
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\DoxyCodeLine{03646\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC\_C2-\/>AHB3ENR,\ RCC\_AHB3ENR\_DMA2DEN);\(\backslash\)}}
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\DoxyCodeLine{03651\ }
\DoxyCodeLine{03652\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_JPGDECEN\_CLK\_ENABLE()\ \ \ do\ \{\ \(\backslash\)}}
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\DoxyCodeLine{03659\ }
\DoxyCodeLine{03660\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_FLASH\_C2\_ALLOCATE()\ \ \ do\ \{\ \(\backslash\)}}
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\DoxyCodeLine{03667\ }
\DoxyCodeLine{03668\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_DTCM1\_C2\_ALLOCATE()\ \ \ do\ \{\ \(\backslash\)}}
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\DoxyCodeLine{03670\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC\_C2-\/>AHB3ENR,\ RCC\_AHB3ENR\_DTCM1EN);\(\backslash\)}}
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\DoxyCodeLine{03675\ }
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\DoxyCodeLine{03678\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC\_C2-\/>AHB3ENR,\ RCC\_AHB3ENR\_DTCM2EN);\(\backslash\)}}
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\DoxyCodeLine{03681\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ UNUSED(tmpreg);\ \(\backslash\)}}
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\DoxyCodeLine{03683\ }
\DoxyCodeLine{03684\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_ITCM\_C2\_ALLOCATE()\ \ \ do\ \{\ \(\backslash\)}}
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\DoxyCodeLine{03686\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC\_C2-\/>AHB3ENR,\ RCC\_AHB3ENR\_ITCMEN);\(\backslash\)}}
\DoxyCodeLine{03687\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ an\ RCC\ peripheral\ clock\ enabling\ */}\textcolor{preprocessor}{\ \(\backslash\)}}
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\DoxyCodeLine{03711\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ an\ RCC\ peripheral\ clock\ enabling\ */}\textcolor{preprocessor}{\ \(\backslash\)}}
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\DoxyCodeLine{03715\ }
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\DoxyCodeLine{03719\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ an\ RCC\ peripheral\ clock\ enabling\ */}\textcolor{preprocessor}{\ \(\backslash\)}}
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\DoxyCodeLine{03726\ }
\DoxyCodeLine{03727\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_MDMA\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB3ENR\ \&=\ \string~\ (RCC\_AHB3ENR\_MDMAEN))}}
\DoxyCodeLine{03728\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_DMA2D\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB3ENR\ \&=\ \string~\ (RCC\_AHB3ENR\_DMA2DEN))}}
\DoxyCodeLine{03729\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_JPGDECEN\_CLK\_DISABLE()\ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB3ENR\ \&=\ \string~\ (RCC\_AHB3ENR\_JPGDECEN))}}
\DoxyCodeLine{03730\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_FMC\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB3ENR\ \&=\ \string~\ (RCC\_AHB3ENR\_FMCEN))}}
\DoxyCodeLine{03731\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_QSPI\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB3ENR\ \&=\ \string~\ (RCC\_AHB3ENR\_QSPIEN))}}
\DoxyCodeLine{03732\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_SDMMC1\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB3ENR\ \&=\ \string~\ (RCC\_AHB3ENR\_SDMMC1EN))}}
\DoxyCodeLine{03733\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_FLASH\_C2\_DEALLOCATE()\ \ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB3ENR\ \&=\ \string~\ (RCC\_AHB3ENR\_FLASHEN))}}
\DoxyCodeLine{03734\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_DTCM1\_C2\_DEALLOCATE()\ \ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB3ENR\ \&=\ \string~\ (RCC\_AHB3ENR\_DTCM1EN))}}
\DoxyCodeLine{03735\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_DTCM2\_C2\_DEALLOCATE()\ \ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB3ENR\ \&=\ \string~\ (RCC\_AHB3ENR\_DTCM2EN))}}
\DoxyCodeLine{03736\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_ITCM\_C2\_DEALLOCATE()\ \ \ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB3ENR\ \&=\ \string~\ (RCC\_AHB3ENR\_ITCMEN))}}
\DoxyCodeLine{03737\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_D1SRAM1\_C2\_DEALLOCATE()\ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB3ENR\ \&=\ \string~\ (RCC\_AHB3ENR\_AXISRAMEN))}}
\DoxyCodeLine{03738\ }
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\DoxyCodeLine{03760\ }
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\DoxyCodeLine{03776\ }
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\DoxyCodeLine{03784\ }
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\DoxyCodeLine{03792\ }
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\DoxyCodeLine{03800\ }
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\DoxyCodeLine{03808\ }
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\DoxyCodeLine{03812\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ an\ RCC\ peripheral\ clock\ enabling\ */}\textcolor{preprocessor}{\ \(\backslash\)}}
\DoxyCodeLine{03813\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC\_C2-\/>AHB1ENR,\ RCC\_AHB1ENR\_USB1OTGHSULPIEN);\(\backslash\)}}
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\DoxyCodeLine{03819\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC\_C2-\/>AHB1ENR,\ RCC\_AHB1ENR\_USB2OTGHSEN);\(\backslash\)}}
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\DoxyCodeLine{03821\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC\_C2-\/>AHB1ENR,\ RCC\_AHB1ENR\_USB2OTGHSEN);\(\backslash\)}}
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\DoxyCodeLine{03824\ }
\DoxyCodeLine{03825\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_USB2\_OTG\_FS\_ULPI\_CLK\_ENABLE()\ \ \ do\ \{\ \(\backslash\)}}
\DoxyCodeLine{03826\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_IO\ uint32\_t\ tmpreg;\ \(\backslash\)}}
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\DoxyCodeLine{03828\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ an\ RCC\ peripheral\ clock\ enabling\ */}\textcolor{preprocessor}{\ \(\backslash\)}}
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\DoxyCodeLine{03832\ }
\DoxyCodeLine{03833\ }
\DoxyCodeLine{03834\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_DMA1\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB1ENR\ \&=\ \string~\ (RCC\_AHB1ENR\_DMA1EN))}}
\DoxyCodeLine{03835\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_DMA2\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB1ENR\ \&=\ \string~\ (RCC\_AHB1ENR\_DMA2EN))}}
\DoxyCodeLine{03836\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_ADC12\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB1ENR\ \&=\ \string~\ (RCC\_AHB1ENR\_ADC12EN))}}
\DoxyCodeLine{03837\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_ART\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB1ENR\ \&=\ \string~\ (RCC\_AHB1ENR\_ARTEN))}}
\DoxyCodeLine{03838\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_ETH1MAC\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB1ENR\ \&=\ \string~\ (RCC\_AHB1ENR\_ETH1MACEN))}}
\DoxyCodeLine{03839\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_ETH1TX\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB1ENR\ \&=\ \string~\ (RCC\_AHB1ENR\_ETH1TXEN))}}
\DoxyCodeLine{03840\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_ETH1RX\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB1ENR\ \&=\ \string~\ (RCC\_AHB1ENR\_ETH1RXEN))}}
\DoxyCodeLine{03841\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_USB1\_OTG\_HS\_CLK\_DISABLE()\ \ \ \ \ \ (RCC\_C2-\/>AHB1ENR\ \&=\ \string~\ (RCC\_AHB1ENR\_USB1OTGHSEN))}}
\DoxyCodeLine{03842\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_USB1\_OTG\_HS\_ULPI\_CLK\_DISABLE()\ (RCC\_C2-\/>AHB1ENR\ \&=\ \string~\ (RCC\_AHB1ENR\_USB1OTGHSULPIEN))}}
\DoxyCodeLine{03843\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_USB2\_OTG\_FS\_CLK\_DISABLE()\ \ \ \ \ \ (RCC\_C2-\/>AHB1ENR\ \&=\ \string~\ (RCC\_AHB1ENR\_USB2OTGHSEN))}}
\DoxyCodeLine{03844\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_USB2\_OTG\_FS\_ULPI\_CLK\_DISABLE()\ (RCC\_C2-\/>AHB1ENR\ \&=\ \string~\ (RCC\_AHB1ENR\_USB2OTGHSULPIEN))}}
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\DoxyCodeLine{03851\ }
\DoxyCodeLine{03852\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_DCMI\_CLK\_ENABLE()\ \ \ do\ \{\ \(\backslash\)}}
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\DoxyCodeLine{03860\ \textcolor{preprocessor}{\#if\ defined(CRYP)}}
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\DoxyCodeLine{03863\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC\_C2-\/>AHB2ENR,\ RCC\_AHB2ENR\_CRYPEN);\(\backslash\)}}
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\DoxyCodeLine{03868\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ CRYP\ */}\textcolor{preprocessor}{}}
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\DoxyCodeLine{03870\ \textcolor{preprocessor}{\#if\ defined(HASH)}}
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\DoxyCodeLine{03878\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ HASH\ */}\textcolor{preprocessor}{}}
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\DoxyCodeLine{03880\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_RNG\_CLK\_ENABLE()\ \ \ do\ \{\ \(\backslash\)}}
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\DoxyCodeLine{03882\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC\_C2-\/>AHB2ENR,\ RCC\_AHB2ENR\_RNGEN);\(\backslash\)}}
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\DoxyCodeLine{03887\ }
\DoxyCodeLine{03888\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_SDMMC2\_CLK\_ENABLE()\ \ \ do\ \{\ \(\backslash\)}}
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\DoxyCodeLine{03890\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC\_C2-\/>AHB2ENR,\ RCC\_AHB2ENR\_SDMMC2EN);\(\backslash\)}}
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\DoxyCodeLine{03892\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC\_C2-\/>AHB2ENR,\ RCC\_AHB2ENR\_SDMMC2EN);\(\backslash\)}}
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\DoxyCodeLine{03895\ }
\DoxyCodeLine{03896\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_D2SRAM1\_CLK\_ENABLE()\ \ \ do\ \{\ \(\backslash\)}}
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\DoxyCodeLine{03898\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC\_C2-\/>AHB2ENR,\ RCC\_AHB2ENR\_D2SRAM1EN);\(\backslash\)}}
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\DoxyCodeLine{03900\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC\_C2-\/>AHB2ENR,\ RCC\_AHB2ENR\_D2SRAM1EN);\(\backslash\)}}
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\DoxyCodeLine{03903\ }
\DoxyCodeLine{03904\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_D2SRAM2\_CLK\_ENABLE()\ \ \ do\ \{\ \(\backslash\)}}
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\DoxyCodeLine{03906\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC\_C2-\/>AHB2ENR,\ RCC\_AHB2ENR\_D2SRAM2EN);\(\backslash\)}}
\DoxyCodeLine{03907\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ an\ RCC\ peripheral\ clock\ enabling\ */}\textcolor{preprocessor}{\ \(\backslash\)}}
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\DoxyCodeLine{03911\ }
\DoxyCodeLine{03912\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_D2SRAM3\_CLK\_ENABLE()\ \ \ do\ \{\ \(\backslash\)}}
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\DoxyCodeLine{03915\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ an\ RCC\ peripheral\ clock\ enabling\ */}\textcolor{preprocessor}{\ \(\backslash\)}}
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\DoxyCodeLine{03919\ }
\DoxyCodeLine{03920\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_DCMI\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB2ENR\ \&=\ \string~\ (RCC\_AHB2ENR\_DCMIEN))}}
\DoxyCodeLine{03921\ \textcolor{preprocessor}{\#if\ defined(CRYP)}}
\DoxyCodeLine{03922\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_CRYP\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB2ENR\ \&=\ \string~\ (RCC\_AHB2ENR\_CRYPEN))}}
\DoxyCodeLine{03923\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ CRYP\ */}\textcolor{preprocessor}{}}
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\DoxyCodeLine{03927\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_RNG\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB2ENR\ \&=\ \string~\ (RCC\_AHB2ENR\_RNGEN))}}
\DoxyCodeLine{03928\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_SDMMC2\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB2ENR\ \&=\ \string~\ (RCC\_AHB2ENR\_SDMMC2EN))}}
\DoxyCodeLine{03929\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_D2SRAM1\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB2ENR\ \&=\ \string~\ (RCC\_AHB2ENR\_D2SRAM1EN))}}
\DoxyCodeLine{03930\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_D2SRAM2\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB2ENR\ \&=\ \string~\ (RCC\_AHB2ENR\_D2SRAM2EN))}}
\DoxyCodeLine{03931\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_D2SRAM3\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB2ENR\ \&=\ \string~\ (RCC\_AHB2ENR\_D2SRAM3EN))}}
\DoxyCodeLine{03932\ }
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\DoxyCodeLine{03939\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_GPIOA\_CLK\_ENABLE()\ \ \ do\ \{\ \(\backslash\)}}
\DoxyCodeLine{03940\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_IO\ uint32\_t\ tmpreg;\ \(\backslash\)}}
\DoxyCodeLine{03941\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC\_C2-\/>AHB4ENR,\ RCC\_AHB4ENR\_GPIOAEN);\(\backslash\)}}
\DoxyCodeLine{03942\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ an\ RCC\ peripheral\ clock\ enabling\ */}\textcolor{preprocessor}{\ \(\backslash\)}}
\DoxyCodeLine{03943\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC\_C2-\/>AHB4ENR,\ RCC\_AHB4ENR\_GPIOAEN);\(\backslash\)}}
\DoxyCodeLine{03944\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ UNUSED(tmpreg);\ \(\backslash\)}}
\DoxyCodeLine{03945\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ while(0)}}
\DoxyCodeLine{03946\ }
\DoxyCodeLine{03947\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_GPIOB\_CLK\_ENABLE()\ \ \ do\ \{\ \(\backslash\)}}
\DoxyCodeLine{03948\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_IO\ uint32\_t\ tmpreg;\ \(\backslash\)}}
\DoxyCodeLine{03949\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC\_C2-\/>AHB4ENR,\ RCC\_AHB4ENR\_GPIOBEN);\(\backslash\)}}
\DoxyCodeLine{03950\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ an\ RCC\ peripheral\ clock\ enabling\ */}\textcolor{preprocessor}{\ \(\backslash\)}}
\DoxyCodeLine{03951\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC\_C2-\/>AHB4ENR,\ RCC\_AHB4ENR\_GPIOBEN);\(\backslash\)}}
\DoxyCodeLine{03952\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ UNUSED(tmpreg);\ \(\backslash\)}}
\DoxyCodeLine{03953\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ while(0)}}
\DoxyCodeLine{03954\ }
\DoxyCodeLine{03955\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_GPIOC\_CLK\_ENABLE()\ \ \ do\ \{\ \(\backslash\)}}
\DoxyCodeLine{03956\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_IO\ uint32\_t\ tmpreg;\ \(\backslash\)}}
\DoxyCodeLine{03957\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC\_C2-\/>AHB4ENR,\ RCC\_AHB4ENR\_GPIOCEN);\(\backslash\)}}
\DoxyCodeLine{03958\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ an\ RCC\ peripheral\ clock\ enabling\ */}\textcolor{preprocessor}{\ \(\backslash\)}}
\DoxyCodeLine{03959\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC\_C2-\/>AHB4ENR,\ RCC\_AHB4ENR\_GPIOCEN);\(\backslash\)}}
\DoxyCodeLine{03960\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ UNUSED(tmpreg);\ \(\backslash\)}}
\DoxyCodeLine{03961\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ while(0)}}
\DoxyCodeLine{03962\ }
\DoxyCodeLine{03963\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_GPIOD\_CLK\_ENABLE()\ \ \ do\ \{\ \(\backslash\)}}
\DoxyCodeLine{03964\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_IO\ uint32\_t\ tmpreg;\ \(\backslash\)}}
\DoxyCodeLine{03965\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC\_C2-\/>AHB4ENR,\ RCC\_AHB4ENR\_GPIODEN);\(\backslash\)}}
\DoxyCodeLine{03966\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ an\ RCC\ peripheral\ clock\ enabling\ */}\textcolor{preprocessor}{\ \(\backslash\)}}
\DoxyCodeLine{03967\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC\_C2-\/>AHB4ENR,\ RCC\_AHB4ENR\_GPIODEN);\(\backslash\)}}
\DoxyCodeLine{03968\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ UNUSED(tmpreg);\ \(\backslash\)}}
\DoxyCodeLine{03969\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ while(0)}}
\DoxyCodeLine{03970\ }
\DoxyCodeLine{03971\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_GPIOE\_CLK\_ENABLE()\ \ \ do\ \{\ \(\backslash\)}}
\DoxyCodeLine{03972\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_IO\ uint32\_t\ tmpreg;\ \(\backslash\)}}
\DoxyCodeLine{03973\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC\_C2-\/>AHB4ENR,\ RCC\_AHB4ENR\_GPIOEEN);\(\backslash\)}}
\DoxyCodeLine{03974\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ an\ RCC\ peripheral\ clock\ enabling\ */}\textcolor{preprocessor}{\ \(\backslash\)}}
\DoxyCodeLine{03975\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC\_C2-\/>AHB4ENR,\ RCC\_AHB4ENR\_GPIOEEN);\(\backslash\)}}
\DoxyCodeLine{03976\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ UNUSED(tmpreg);\ \(\backslash\)}}
\DoxyCodeLine{03977\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ while(0)}}
\DoxyCodeLine{03978\ }
\DoxyCodeLine{03979\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_GPIOF\_CLK\_ENABLE()\ \ \ do\ \{\ \(\backslash\)}}
\DoxyCodeLine{03980\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_IO\ uint32\_t\ tmpreg;\ \(\backslash\)}}
\DoxyCodeLine{03981\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC\_C2-\/>AHB4ENR,\ RCC\_AHB4ENR\_GPIOFEN);\(\backslash\)}}
\DoxyCodeLine{03982\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ an\ RCC\ peripheral\ clock\ enabling\ */}\textcolor{preprocessor}{\ \(\backslash\)}}
\DoxyCodeLine{03983\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC\_C2-\/>AHB4ENR,\ RCC\_AHB4ENR\_GPIOFEN);\(\backslash\)}}
\DoxyCodeLine{03984\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ UNUSED(tmpreg);\ \(\backslash\)}}
\DoxyCodeLine{03985\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ while(0)}}
\DoxyCodeLine{03986\ }
\DoxyCodeLine{03987\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_GPIOG\_CLK\_ENABLE()\ \ \ do\ \{\ \(\backslash\)}}
\DoxyCodeLine{03988\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_IO\ uint32\_t\ tmpreg;\ \(\backslash\)}}
\DoxyCodeLine{03989\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC\_C2-\/>AHB4ENR,\ RCC\_AHB4ENR\_GPIOGEN);\(\backslash\)}}
\DoxyCodeLine{03990\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ an\ RCC\ peripheral\ clock\ enabling\ */}\textcolor{preprocessor}{\ \(\backslash\)}}
\DoxyCodeLine{03991\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC\_C2-\/>AHB4ENR,\ RCC\_AHB4ENR\_GPIOGEN);\(\backslash\)}}
\DoxyCodeLine{03992\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ UNUSED(tmpreg);\ \(\backslash\)}}
\DoxyCodeLine{03993\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ while(0)}}
\DoxyCodeLine{03994\ }
\DoxyCodeLine{03995\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_GPIOH\_CLK\_ENABLE()\ \ \ do\ \{\ \(\backslash\)}}
\DoxyCodeLine{03996\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_IO\ uint32\_t\ tmpreg;\ \(\backslash\)}}
\DoxyCodeLine{03997\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC\_C2-\/>AHB4ENR,\ RCC\_AHB4ENR\_GPIOHEN);\(\backslash\)}}
\DoxyCodeLine{03998\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ an\ RCC\ peripheral\ clock\ enabling\ */}\textcolor{preprocessor}{\ \(\backslash\)}}
\DoxyCodeLine{03999\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC\_C2-\/>AHB4ENR,\ RCC\_AHB4ENR\_GPIOHEN);\(\backslash\)}}
\DoxyCodeLine{04000\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ UNUSED(tmpreg);\ \(\backslash\)}}
\DoxyCodeLine{04001\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ while(0)}}
\DoxyCodeLine{04002\ }
\DoxyCodeLine{04003\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_GPIOI\_CLK\_ENABLE()\ \ \ do\ \{\ \(\backslash\)}}
\DoxyCodeLine{04004\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_IO\ uint32\_t\ tmpreg;\ \(\backslash\)}}
\DoxyCodeLine{04005\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC\_C2-\/>AHB4ENR,\ RCC\_AHB4ENR\_GPIOIEN);\(\backslash\)}}
\DoxyCodeLine{04006\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ an\ RCC\ peripheral\ clock\ enabling\ */}\textcolor{preprocessor}{\ \(\backslash\)}}
\DoxyCodeLine{04007\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC\_C2-\/>AHB4ENR,\ RCC\_AHB4ENR\_GPIOIEN);\(\backslash\)}}
\DoxyCodeLine{04008\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ UNUSED(tmpreg);\ \(\backslash\)}}
\DoxyCodeLine{04009\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ while(0)}}
\DoxyCodeLine{04010\ }
\DoxyCodeLine{04011\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_GPIOJ\_CLK\_ENABLE()\ \ \ do\ \{\ \(\backslash\)}}
\DoxyCodeLine{04012\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_IO\ uint32\_t\ tmpreg;\ \(\backslash\)}}
\DoxyCodeLine{04013\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC\_C2-\/>AHB4ENR,\ RCC\_AHB4ENR\_GPIOJEN);\(\backslash\)}}
\DoxyCodeLine{04014\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ an\ RCC\ peripheral\ clock\ enabling\ */}\textcolor{preprocessor}{\ \(\backslash\)}}
\DoxyCodeLine{04015\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC\_C2-\/>AHB4ENR,\ RCC\_AHB4ENR\_GPIOJEN);\(\backslash\)}}
\DoxyCodeLine{04016\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ UNUSED(tmpreg);\ \(\backslash\)}}
\DoxyCodeLine{04017\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ while(0)}}
\DoxyCodeLine{04018\ }
\DoxyCodeLine{04019\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_GPIOK\_CLK\_ENABLE()\ \ \ do\ \{\ \(\backslash\)}}
\DoxyCodeLine{04020\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_IO\ uint32\_t\ tmpreg;\ \(\backslash\)}}
\DoxyCodeLine{04021\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC\_C2-\/>AHB4ENR,\ RCC\_AHB4ENR\_GPIOKEN);\(\backslash\)}}
\DoxyCodeLine{04022\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ an\ RCC\ peripheral\ clock\ enabling\ */}\textcolor{preprocessor}{\ \(\backslash\)}}
\DoxyCodeLine{04023\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC\_C2-\/>AHB4ENR,\ RCC\_AHB4ENR\_GPIOKEN);\(\backslash\)}}
\DoxyCodeLine{04024\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ UNUSED(tmpreg);\ \(\backslash\)}}
\DoxyCodeLine{04025\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ while(0)}}
\DoxyCodeLine{04026\ }
\DoxyCodeLine{04027\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_CRC\_CLK\_ENABLE()\ \ \ do\ \{\ \(\backslash\)}}
\DoxyCodeLine{04028\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_IO\ uint32\_t\ tmpreg;\ \(\backslash\)}}
\DoxyCodeLine{04029\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC\_C2-\/>AHB4ENR,\ RCC\_AHB4ENR\_CRCEN);\(\backslash\)}}
\DoxyCodeLine{04030\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ an\ RCC\ peripheral\ clock\ enabling\ */}\textcolor{preprocessor}{\ \(\backslash\)}}
\DoxyCodeLine{04031\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC\_C2-\/>AHB4ENR,\ RCC\_AHB4ENR\_CRCEN);\(\backslash\)}}
\DoxyCodeLine{04032\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ UNUSED(tmpreg);\ \(\backslash\)}}
\DoxyCodeLine{04033\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ while(0)}}
\DoxyCodeLine{04034\ }
\DoxyCodeLine{04035\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_BDMA\_CLK\_ENABLE()\ \ \ do\ \{\ \(\backslash\)}}
\DoxyCodeLine{04036\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_IO\ uint32\_t\ tmpreg;\ \(\backslash\)}}
\DoxyCodeLine{04037\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC\_C2-\/>AHB4ENR,\ RCC\_AHB4ENR\_BDMAEN);\(\backslash\)}}
\DoxyCodeLine{04038\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ an\ RCC\ peripheral\ clock\ enabling\ */}\textcolor{preprocessor}{\ \(\backslash\)}}
\DoxyCodeLine{04039\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC\_C2-\/>AHB4ENR,\ RCC\_AHB4ENR\_BDMAEN);\(\backslash\)}}
\DoxyCodeLine{04040\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ UNUSED(tmpreg);\ \(\backslash\)}}
\DoxyCodeLine{04041\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ while(0)}}
\DoxyCodeLine{04042\ }
\DoxyCodeLine{04043\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_ADC3\_CLK\_ENABLE()\ \ \ do\ \{\ \(\backslash\)}}
\DoxyCodeLine{04044\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_IO\ uint32\_t\ tmpreg;\ \(\backslash\)}}
\DoxyCodeLine{04045\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC\_C2-\/>AHB4ENR,\ RCC\_AHB4ENR\_ADC3EN);\(\backslash\)}}
\DoxyCodeLine{04046\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ an\ RCC\ peripheral\ clock\ enabling\ */}\textcolor{preprocessor}{\ \(\backslash\)}}
\DoxyCodeLine{04047\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC\_C2-\/>AHB4ENR,\ RCC\_AHB4ENR\_ADC3EN);\(\backslash\)}}
\DoxyCodeLine{04048\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ UNUSED(tmpreg);\ \(\backslash\)}}
\DoxyCodeLine{04049\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ while(0)}}
\DoxyCodeLine{04050\ }
\DoxyCodeLine{04051\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_HSEM\_CLK\_ENABLE()\ \ \ do\ \{\ \(\backslash\)}}
\DoxyCodeLine{04052\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_IO\ uint32\_t\ tmpreg;\ \(\backslash\)}}
\DoxyCodeLine{04053\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC\_C2-\/>AHB4ENR,\ RCC\_AHB4ENR\_HSEMEN);\(\backslash\)}}
\DoxyCodeLine{04054\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ an\ RCC\ peripheral\ clock\ enabling\ */}\textcolor{preprocessor}{\ \(\backslash\)}}
\DoxyCodeLine{04055\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC\_C2-\/>AHB4ENR,\ RCC\_AHB4ENR\_HSEMEN);\(\backslash\)}}
\DoxyCodeLine{04056\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ UNUSED(tmpreg);\ \(\backslash\)}}
\DoxyCodeLine{04057\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ while(0)}}
\DoxyCodeLine{04058\ }
\DoxyCodeLine{04059\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_BKPRAM\_CLK\_ENABLE()\ \ \ do\ \{\ \(\backslash\)}}
\DoxyCodeLine{04060\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_IO\ uint32\_t\ tmpreg;\ \(\backslash\)}}
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\DoxyCodeLine{04063\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC\_C2-\/>AHB4ENR,\ RCC\_AHB4ENR\_BKPRAMEN);\(\backslash\)}}
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\DoxyCodeLine{04066\ }
\DoxyCodeLine{04067\ }
\DoxyCodeLine{04068\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_GPIOA\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB4ENR)\ \&=\ \string~\ (RCC\_AHB4ENR\_GPIOAEN)}}
\DoxyCodeLine{04069\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_GPIOB\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB4ENR)\ \&=\ \string~\ (RCC\_AHB4ENR\_GPIOBEN)}}
\DoxyCodeLine{04070\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_GPIOC\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB4ENR)\ \&=\ \string~\ (RCC\_AHB4ENR\_GPIOCEN)}}
\DoxyCodeLine{04071\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_GPIOD\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB4ENR)\ \&=\ \string~\ (RCC\_AHB4ENR\_GPIODEN)}}
\DoxyCodeLine{04072\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_GPIOE\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB4ENR)\ \&=\ \string~\ (RCC\_AHB4ENR\_GPIOEEN)}}
\DoxyCodeLine{04073\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_GPIOF\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB4ENR)\ \&=\ \string~\ (RCC\_AHB4ENR\_GPIOFEN)}}
\DoxyCodeLine{04074\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_GPIOG\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB4ENR)\ \&=\ \string~\ (RCC\_AHB4ENR\_GPIOGEN)}}
\DoxyCodeLine{04075\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_GPIOH\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB4ENR)\ \&=\ \string~\ (RCC\_AHB4ENR\_GPIOHEN)}}
\DoxyCodeLine{04076\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_GPIOI\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB4ENR)\ \&=\ \string~\ (RCC\_AHB4ENR\_GPIOIEN)}}
\DoxyCodeLine{04077\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_GPIOJ\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB4ENR)\ \&=\ \string~\ (RCC\_AHB4ENR\_GPIOJEN)}}
\DoxyCodeLine{04078\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_GPIOK\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB4ENR)\ \&=\ \string~\ (RCC\_AHB4ENR\_GPIOKEN)}}
\DoxyCodeLine{04079\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_CRC\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB4ENR)\ \&=\ \string~\ (RCC\_AHB4ENR\_CRCEN)}}
\DoxyCodeLine{04080\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_BDMA\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB4ENR)\ \&=\ \string~\ (RCC\_AHB4ENR\_BDMAEN)}}
\DoxyCodeLine{04081\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_ADC3\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB4ENR)\ \&=\ \string~\ (RCC\_AHB4ENR\_ADC3EN)}}
\DoxyCodeLine{04082\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_HSEM\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB4ENR)\ \&=\ \string~\ (RCC\_AHB4ENR\_HSEMEN)}}
\DoxyCodeLine{04083\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_BKPRAM\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB4ENR)\ \&=\ \string~\ (RCC\_AHB4ENR\_BKPRAMEN)}}
\DoxyCodeLine{04084\ }
\DoxyCodeLine{04085\ }
\DoxyCodeLine{04091\ }
\DoxyCodeLine{04092\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_LTDC\_CLK\_ENABLE()\ \ \ do\ \{\ \(\backslash\)}}
\DoxyCodeLine{04093\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_IO\ uint32\_t\ tmpreg;\ \(\backslash\)}}
\DoxyCodeLine{04094\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC\_C2-\/>APB3ENR,\ RCC\_APB3ENR\_LTDCEN);\(\backslash\)}}
\DoxyCodeLine{04095\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ an\ RCC\ peripheral\ clock\ enabling\ */}\textcolor{preprocessor}{\ \(\backslash\)}}
\DoxyCodeLine{04096\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC\_C2-\/>APB3ENR,\ RCC\_APB3ENR\_LTDCEN);\(\backslash\)}}
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\DoxyCodeLine{04098\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ while(0)}}
\DoxyCodeLine{04099\ }
\DoxyCodeLine{04100\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_DSI\_CLK\_ENABLE()\ \ \ do\ \{\ \(\backslash\)}}
\DoxyCodeLine{04101\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_IO\ uint32\_t\ tmpreg;\ \(\backslash\)}}
\DoxyCodeLine{04102\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC\_C2-\/>APB3ENR,\ RCC\_APB3ENR\_DSIEN);\(\backslash\)}}
\DoxyCodeLine{04103\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ an\ RCC\ peripheral\ clock\ enabling\ */}\textcolor{preprocessor}{\ \(\backslash\)}}
\DoxyCodeLine{04104\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC\_C2-\/>APB3ENR,\ RCC\_APB3ENR\_DSIEN);\(\backslash\)}}
\DoxyCodeLine{04105\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ UNUSED(tmpreg);\ \(\backslash\)}}
\DoxyCodeLine{04106\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ while(0)}}
\DoxyCodeLine{04107\ }
\DoxyCodeLine{04108\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_WWDG1\_CLK\_ENABLE()\ \ \ do\ \{\ \(\backslash\)}}
\DoxyCodeLine{04109\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_IO\ uint32\_t\ tmpreg;\ \(\backslash\)}}
\DoxyCodeLine{04110\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC\_C2-\/>APB3ENR,\ RCC\_APB3ENR\_WWDG1EN);\(\backslash\)}}
\DoxyCodeLine{04111\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ an\ RCC\ peripheral\ clock\ enabling\ */}\textcolor{preprocessor}{\ \(\backslash\)}}
\DoxyCodeLine{04112\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC\_C2-\/>APB3ENR,\ RCC\_APB3ENR\_WWDG1EN);\(\backslash\)}}
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\DoxyCodeLine{04115\ }
\DoxyCodeLine{04116\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_LTDC\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>APB3ENR)\ \&=\ \string~\ (RCC\_APB3ENR\_LTDCEN)}}
\DoxyCodeLine{04117\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_DSI\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>APB3ENR)\ \&=\ \string~\ (RCC\_APB3ENR\_DSIEN)}}
\DoxyCodeLine{04118\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_WWDG1\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>APB3ENR)\ \&=\ \string~\ (RCC\_APB3ENR\_WWDG1EN)}}
\DoxyCodeLine{04119\ }
\DoxyCodeLine{04125\ }
\DoxyCodeLine{04126\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_TIM2\_CLK\_ENABLE()\ \ \ do\ \{\ \(\backslash\)}}
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\DoxyCodeLine{04128\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC\_C2-\/>APB1LENR,\ RCC\_APB1LENR\_TIM2EN);\(\backslash\)}}
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\DoxyCodeLine{04130\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC\_C2-\/>APB1LENR,\ RCC\_APB1LENR\_TIM2EN);\(\backslash\)}}
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\DoxyCodeLine{04133\ }
\DoxyCodeLine{04134\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_TIM3\_CLK\_ENABLE()\ \ \ do\ \{\ \(\backslash\)}}
\DoxyCodeLine{04135\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_IO\ uint32\_t\ tmpreg;\ \(\backslash\)}}
\DoxyCodeLine{04136\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC\_C2-\/>APB1LENR,\ RCC\_APB1LENR\_TIM3EN);\(\backslash\)}}
\DoxyCodeLine{04137\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ an\ RCC\ peripheral\ clock\ enabling\ */}\textcolor{preprocessor}{\ \(\backslash\)}}
\DoxyCodeLine{04138\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC\_C2-\/>APB1LENR,\ RCC\_APB1LENR\_TIM3EN);\(\backslash\)}}
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\DoxyCodeLine{04141\ }
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\DoxyCodeLine{04143\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_IO\ uint32\_t\ tmpreg;\ \(\backslash\)}}
\DoxyCodeLine{04144\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC\_C2-\/>APB1LENR,\ RCC\_APB1LENR\_TIM4EN);\(\backslash\)}}
\DoxyCodeLine{04145\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ an\ RCC\ peripheral\ clock\ enabling\ */}\textcolor{preprocessor}{\ \(\backslash\)}}
\DoxyCodeLine{04146\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC\_C2-\/>APB1LENR,\ RCC\_APB1LENR\_TIM4EN);\(\backslash\)}}
\DoxyCodeLine{04147\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ UNUSED(tmpreg);\ \(\backslash\)}}
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\DoxyCodeLine{04149\ }
\DoxyCodeLine{04150\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_TIM5\_CLK\_ENABLE()\ \ \ do\ \{\ \(\backslash\)}}
\DoxyCodeLine{04151\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_IO\ uint32\_t\ tmpreg;\ \(\backslash\)}}
\DoxyCodeLine{04152\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC\_C2-\/>APB1LENR,\ RCC\_APB1LENR\_TIM5EN);\(\backslash\)}}
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\DoxyCodeLine{04154\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC\_C2-\/>APB1LENR,\ RCC\_APB1LENR\_TIM5EN);\(\backslash\)}}
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\DoxyCodeLine{04157\ }
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\DoxyCodeLine{04159\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_IO\ uint32\_t\ tmpreg;\ \(\backslash\)}}
\DoxyCodeLine{04160\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC\_C2-\/>APB1LENR,\ RCC\_APB1LENR\_TIM6EN);\(\backslash\)}}
\DoxyCodeLine{04161\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ an\ RCC\ peripheral\ clock\ enabling\ */}\textcolor{preprocessor}{\ \(\backslash\)}}
\DoxyCodeLine{04162\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC\_C2-\/>APB1LENR,\ RCC\_APB1LENR\_TIM6EN);\(\backslash\)}}
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\DoxyCodeLine{04165\ }
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\DoxyCodeLine{04170\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC\_C2-\/>APB1LENR,\ RCC\_APB1LENR\_TIM7EN);\(\backslash\)}}
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\DoxyCodeLine{04173\ }
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\DoxyCodeLine{04181\ }
\DoxyCodeLine{04182\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_TIM13\_CLK\_ENABLE()\ \ \ do\ \{\ \(\backslash\)}}
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\DoxyCodeLine{04186\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC\_C2-\/>APB1LENR,\ RCC\_APB1LENR\_TIM13EN);\(\backslash\)}}
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\DoxyCodeLine{04205\ }
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\DoxyCodeLine{04237\ }
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\DoxyCodeLine{04382\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_USART3\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ (RCC\_C2-\/>APB1LENR)\ \&=\ \string~\ (RCC\_APB1LENR\_USART3EN)}}
\DoxyCodeLine{04383\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_UART4\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>APB1LENR)\ \&=\ \string~\ (RCC\_APB1LENR\_UART4EN)}}
\DoxyCodeLine{04384\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_UART5\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>APB1LENR)\ \&=\ \string~\ (RCC\_APB1LENR\_UART5EN)}}
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\DoxyCodeLine{04388\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_CEC\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>APB1LENR)\ \&=\ \string~\ (RCC\_APB1LENR\_CECEN)}}
\DoxyCodeLine{04389\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_DAC12\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>APB1LENR)\ \&=\ \string~\ (RCC\_APB1LENR\_DAC12EN)}}
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\DoxyCodeLine{04393\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_SWPMI\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>APB1HENR)\ \&=\ \string~\ (RCC\_APB1HENR\_SWPMIEN)}}
\DoxyCodeLine{04394\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_OPAMP\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>APB1HENR)\ \&=\ \string~\ (RCC\_APB1HENR\_OPAMPEN)}}
\DoxyCodeLine{04395\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_MDIOS\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>APB1HENR)\ \&=\ \string~\ (RCC\_APB1HENR\_MDIOSEN)}}
\DoxyCodeLine{04396\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_FDCAN\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>APB1HENR)\ \&=\ \string~\ (RCC\_APB1HENR\_FDCANEN)}}
\DoxyCodeLine{04397\ }
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\DoxyCodeLine{04427\ }
\DoxyCodeLine{04428\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_USART6\_CLK\_ENABLE()\ \ \ do\ \{\ \(\backslash\)}}
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\DoxyCodeLine{04430\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC\_C2-\/>APB2ENR,\ RCC\_APB2ENR\_USART6EN);\(\backslash\)}}
\DoxyCodeLine{04431\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ an\ RCC\ peripheral\ clock\ enabling\ */}\textcolor{preprocessor}{\ \(\backslash\)}}
\DoxyCodeLine{04432\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC\_C2-\/>APB2ENR,\ RCC\_APB2ENR\_USART6EN);\(\backslash\)}}
\DoxyCodeLine{04433\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ UNUSED(tmpreg);\ \(\backslash\)}}
\DoxyCodeLine{04434\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ while(0)}}
\DoxyCodeLine{04435\ }
\DoxyCodeLine{04436\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_SPI1\_CLK\_ENABLE()\ \ \ do\ \{\ \(\backslash\)}}
\DoxyCodeLine{04437\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_IO\ uint32\_t\ tmpreg;\ \(\backslash\)}}
\DoxyCodeLine{04438\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC\_C2-\/>APB2ENR,\ RCC\_APB2ENR\_SPI1EN);\(\backslash\)}}
\DoxyCodeLine{04439\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ an\ RCC\ peripheral\ clock\ enabling\ */}\textcolor{preprocessor}{\ \(\backslash\)}}
\DoxyCodeLine{04440\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC\_C2-\/>APB2ENR,\ RCC\_APB2ENR\_SPI1EN);\(\backslash\)}}
\DoxyCodeLine{04441\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ UNUSED(tmpreg);\ \(\backslash\)}}
\DoxyCodeLine{04442\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ while(0)}}
\DoxyCodeLine{04443\ }
\DoxyCodeLine{04444\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_SPI4\_CLK\_ENABLE()\ \ \ do\ \{\ \(\backslash\)}}
\DoxyCodeLine{04445\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_IO\ uint32\_t\ tmpreg;\ \(\backslash\)}}
\DoxyCodeLine{04446\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC\_C2-\/>APB2ENR,\ RCC\_APB2ENR\_SPI4EN);\(\backslash\)}}
\DoxyCodeLine{04447\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ an\ RCC\ peripheral\ clock\ enabling\ */}\textcolor{preprocessor}{\ \(\backslash\)}}
\DoxyCodeLine{04448\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC\_C2-\/>APB2ENR,\ RCC\_APB2ENR\_SPI4EN);\(\backslash\)}}
\DoxyCodeLine{04449\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ UNUSED(tmpreg);\ \(\backslash\)}}
\DoxyCodeLine{04450\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ while(0)}}
\DoxyCodeLine{04451\ }
\DoxyCodeLine{04452\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_TIM15\_CLK\_ENABLE()\ \ \ do\ \{\ \(\backslash\)}}
\DoxyCodeLine{04453\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_IO\ uint32\_t\ tmpreg;\ \(\backslash\)}}
\DoxyCodeLine{04454\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC\_C2-\/>APB2ENR,\ RCC\_APB2ENR\_TIM15EN);\(\backslash\)}}
\DoxyCodeLine{04455\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ an\ RCC\ peripheral\ clock\ enabling\ */}\textcolor{preprocessor}{\ \(\backslash\)}}
\DoxyCodeLine{04456\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC\_C2-\/>APB2ENR,\ RCC\_APB2ENR\_TIM15EN);\(\backslash\)}}
\DoxyCodeLine{04457\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ UNUSED(tmpreg);\ \(\backslash\)}}
\DoxyCodeLine{04458\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ while(0)}}
\DoxyCodeLine{04459\ }
\DoxyCodeLine{04460\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_TIM16\_CLK\_ENABLE()\ \ \ do\ \{\ \(\backslash\)}}
\DoxyCodeLine{04461\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_IO\ uint32\_t\ tmpreg;\ \(\backslash\)}}
\DoxyCodeLine{04462\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC\_C2-\/>APB2ENR,\ RCC\_APB2ENR\_TIM16EN);\(\backslash\)}}
\DoxyCodeLine{04463\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ an\ RCC\ peripheral\ clock\ enabling\ */}\textcolor{preprocessor}{\ \(\backslash\)}}
\DoxyCodeLine{04464\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC\_C2-\/>APB2ENR,\ RCC\_APB2ENR\_TIM16EN);\(\backslash\)}}
\DoxyCodeLine{04465\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ UNUSED(tmpreg);\ \(\backslash\)}}
\DoxyCodeLine{04466\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ while(0)}}
\DoxyCodeLine{04467\ }
\DoxyCodeLine{04468\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_TIM17\_CLK\_ENABLE()\ \ \ do\ \{\ \(\backslash\)}}
\DoxyCodeLine{04469\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_IO\ uint32\_t\ tmpreg;\ \(\backslash\)}}
\DoxyCodeLine{04470\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC\_C2-\/>APB2ENR,\ RCC\_APB2ENR\_TIM17EN);\(\backslash\)}}
\DoxyCodeLine{04471\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ an\ RCC\ peripheral\ clock\ enabling\ */}\textcolor{preprocessor}{\ \(\backslash\)}}
\DoxyCodeLine{04472\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC\_C2-\/>APB2ENR,\ RCC\_APB2ENR\_TIM17EN);\(\backslash\)}}
\DoxyCodeLine{04473\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ UNUSED(tmpreg);\ \(\backslash\)}}
\DoxyCodeLine{04474\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ while(0)}}
\DoxyCodeLine{04475\ }
\DoxyCodeLine{04476\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_SPI5\_CLK\_ENABLE()\ \ \ do\ \{\ \(\backslash\)}}
\DoxyCodeLine{04477\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_IO\ uint32\_t\ tmpreg;\ \(\backslash\)}}
\DoxyCodeLine{04478\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC\_C2-\/>APB2ENR,\ RCC\_APB2ENR\_SPI5EN);\(\backslash\)}}
\DoxyCodeLine{04479\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ an\ RCC\ peripheral\ clock\ enabling\ */}\textcolor{preprocessor}{\ \(\backslash\)}}
\DoxyCodeLine{04480\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC\_C2-\/>APB2ENR,\ RCC\_APB2ENR\_SPI5EN);\(\backslash\)}}
\DoxyCodeLine{04481\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ UNUSED(tmpreg);\ \(\backslash\)}}
\DoxyCodeLine{04482\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ while(0)}}
\DoxyCodeLine{04483\ }
\DoxyCodeLine{04484\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_SAI1\_CLK\_ENABLE()\ \ \ do\ \{\ \(\backslash\)}}
\DoxyCodeLine{04485\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_IO\ uint32\_t\ tmpreg;\ \(\backslash\)}}
\DoxyCodeLine{04486\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC\_C2-\/>APB2ENR,\ RCC\_APB2ENR\_SAI1EN);\(\backslash\)}}
\DoxyCodeLine{04487\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ an\ RCC\ peripheral\ clock\ enabling\ */}\textcolor{preprocessor}{\ \(\backslash\)}}
\DoxyCodeLine{04488\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC\_C2-\/>APB2ENR,\ RCC\_APB2ENR\_SAI1EN);\(\backslash\)}}
\DoxyCodeLine{04489\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ UNUSED(tmpreg);\ \(\backslash\)}}
\DoxyCodeLine{04490\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ while(0)}}
\DoxyCodeLine{04491\ }
\DoxyCodeLine{04492\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_SAI2\_CLK\_ENABLE()\ \ \ do\ \{\ \(\backslash\)}}
\DoxyCodeLine{04493\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_IO\ uint32\_t\ tmpreg;\ \(\backslash\)}}
\DoxyCodeLine{04494\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC\_C2-\/>APB2ENR,\ RCC\_APB2ENR\_SAI2EN);\(\backslash\)}}
\DoxyCodeLine{04495\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ an\ RCC\ peripheral\ clock\ enabling\ */}\textcolor{preprocessor}{\ \(\backslash\)}}
\DoxyCodeLine{04496\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC\_C2-\/>APB2ENR,\ RCC\_APB2ENR\_SAI2EN);\(\backslash\)}}
\DoxyCodeLine{04497\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ UNUSED(tmpreg);\ \(\backslash\)}}
\DoxyCodeLine{04498\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ while(0)}}
\DoxyCodeLine{04499\ }
\DoxyCodeLine{04500\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_SAI3\_CLK\_ENABLE()\ \ \ do\ \{\ \(\backslash\)}}
\DoxyCodeLine{04501\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_IO\ uint32\_t\ tmpreg;\ \(\backslash\)}}
\DoxyCodeLine{04502\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC\_C2-\/>APB2ENR,\ RCC\_APB2ENR\_SAI3EN);\(\backslash\)}}
\DoxyCodeLine{04503\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ an\ RCC\ peripheral\ clock\ enabling\ */}\textcolor{preprocessor}{\ \(\backslash\)}}
\DoxyCodeLine{04504\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC\_C2-\/>APB2ENR,\ RCC\_APB2ENR\_SAI3EN);\(\backslash\)}}
\DoxyCodeLine{04505\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ UNUSED(tmpreg);\ \(\backslash\)}}
\DoxyCodeLine{04506\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ while(0)}}
\DoxyCodeLine{04507\ }
\DoxyCodeLine{04508\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_DFSDM1\_CLK\_ENABLE()\ \ \ do\ \{\ \(\backslash\)}}
\DoxyCodeLine{04509\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_IO\ uint32\_t\ tmpreg;\ \(\backslash\)}}
\DoxyCodeLine{04510\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC\_C2-\/>APB2ENR,\ RCC\_APB2ENR\_DFSDM1EN);\(\backslash\)}}
\DoxyCodeLine{04511\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ an\ RCC\ peripheral\ clock\ enabling\ */}\textcolor{preprocessor}{\ \(\backslash\)}}
\DoxyCodeLine{04512\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC\_C2-\/>APB2ENR,\ RCC\_APB2ENR\_DFSDM1EN);\(\backslash\)}}
\DoxyCodeLine{04513\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ UNUSED(tmpreg);\ \(\backslash\)}}
\DoxyCodeLine{04514\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ while(0)}}
\DoxyCodeLine{04515\ }
\DoxyCodeLine{04516\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_HRTIM1\_CLK\_ENABLE()\ \ \ do\ \{\ \(\backslash\)}}
\DoxyCodeLine{04517\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_IO\ uint32\_t\ tmpreg;\ \(\backslash\)}}
\DoxyCodeLine{04518\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC\_C2-\/>APB2ENR,\ RCC\_APB2ENR\_HRTIMEN);\(\backslash\)}}
\DoxyCodeLine{04519\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ an\ RCC\ peripheral\ clock\ enabling\ */}\textcolor{preprocessor}{\ \(\backslash\)}}
\DoxyCodeLine{04520\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC\_C2-\/>APB2ENR,\ RCC\_APB2ENR\_HRTIMEN);\(\backslash\)}}
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\DoxyCodeLine{04522\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ while(0)}}
\DoxyCodeLine{04523\ }
\DoxyCodeLine{04524\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_TIM1\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>APB2ENR)\ \&=\ \string~\ (RCC\_APB2ENR\_TIM1EN)}}
\DoxyCodeLine{04525\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_TIM8\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>APB2ENR)\ \&=\ \string~\ (RCC\_APB2ENR\_TIM8EN)}}
\DoxyCodeLine{04526\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_USART1\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ (RCC\_C2-\/>APB2ENR)\ \&=\ \string~\ (RCC\_APB2ENR\_USART1EN)}}
\DoxyCodeLine{04527\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_USART6\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ (RCC\_C2-\/>APB2ENR)\ \&=\ \string~\ (RCC\_APB2ENR\_USART6EN)}}
\DoxyCodeLine{04528\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_SPI1\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>APB2ENR)\ \&=\ \string~\ (RCC\_APB2ENR\_SPI1EN)}}
\DoxyCodeLine{04529\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_SPI4\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>APB2ENR)\ \&=\ \string~\ (RCC\_APB2ENR\_SPI4EN)}}
\DoxyCodeLine{04530\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_TIM15\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>APB2ENR)\ \&=\ \string~\ (RCC\_APB2ENR\_TIM15EN)}}
\DoxyCodeLine{04531\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_TIM16\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>APB2ENR)\ \&=\ \string~\ (RCC\_APB2ENR\_TIM16EN)}}
\DoxyCodeLine{04532\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_TIM17\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>APB2ENR)\ \&=\ \string~\ (RCC\_APB2ENR\_TIM17EN)}}
\DoxyCodeLine{04533\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_SPI5\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>APB2ENR)\ \&=\ \string~\ (RCC\_APB2ENR\_SPI5EN)}}
\DoxyCodeLine{04534\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_SAI1\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>APB2ENR)\ \&=\ \string~\ (RCC\_APB2ENR\_SAI1EN)}}
\DoxyCodeLine{04535\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_SAI2\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>APB2ENR)\ \&=\ \string~\ (RCC\_APB2ENR\_SAI2EN)}}
\DoxyCodeLine{04536\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_SAI3\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>APB2ENR)\ \&=\ \string~\ (RCC\_APB2ENR\_SAI3EN)}}
\DoxyCodeLine{04537\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_DFSDM1\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ (RCC\_C2-\/>APB2ENR)\ \&=\ \string~\ (RCC\_APB2ENR\_DFSDM1EN)}}
\DoxyCodeLine{04538\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_HRTIM1\_CLK\_DISABLE()\ \ \ \ \ \ \ \ \ (RCC\_C2-\/>APB2ENR)\ \&=\ \string~\ (RCC\_APB2ENR\_HRTIMEN)}}
\DoxyCodeLine{04539\ }
\DoxyCodeLine{04545\ }
\DoxyCodeLine{04546\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_SYSCFG\_CLK\_ENABLE()\ \ \ do\ \{\ \(\backslash\)}}
\DoxyCodeLine{04547\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_IO\ uint32\_t\ tmpreg;\ \(\backslash\)}}
\DoxyCodeLine{04548\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC\_C2-\/>APB4ENR,\ RCC\_APB4ENR\_SYSCFGEN);\(\backslash\)}}
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\DoxyCodeLine{04550\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(RCC\_C2-\/>APB4ENR,\ RCC\_APB4ENR\_SYSCFGEN);\(\backslash\)}}
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\DoxyCodeLine{04657\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*DUAL\_CORE*/}\textcolor{preprocessor}{}}
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\DoxyCodeLine{04668\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ STM32H7\_DEV\_ID\ ==\ 0x450UL\ */}\textcolor{preprocessor}{}}
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\DoxyCodeLine{04670\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_DMA2D\_FORCE\_RESET()\ \ \ \ \ \ \ \ \ (RCC-\/>AHB3RSTR\ |=\ (RCC\_AHB3RSTR\_DMA2DRST))}}
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\DoxyCodeLine{04848\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ STM32H7\_DEV\_ID\ ==\ 0x450UL\ */}\textcolor{preprocessor}{}}
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\DoxyCodeLine{04851\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_GPIOC\_FORCE\_RESET()\ \ \ \ \ \ \ \ \ \ \ (RCC-\/>AHB4RSTR)\ |=\ (RCC\_AHB4RSTR\_GPIOCRST)}}
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\DoxyCodeLine{04854\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_GPIOF\_FORCE\_RESET()\ \ \ \ \ \ \ \ \ \ \ (RCC-\/>AHB4RSTR)\ |=\ (RCC\_AHB4RSTR\_GPIOFRST)}}
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\DoxyCodeLine{04860\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_GPIOJ\_FORCE\_RESET()\ \ \ \ \ \ \ \ \ \ \ (RCC-\/>AHB4RSTR)\ |=\ (RCC\_AHB4RSTR\_GPIOJRST)}}
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\DoxyCodeLine{04878\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_AHB4\_RELEASE\_RESET()\ \ \ \ \ \ \ \ \ \ (RCC-\/>AHB4RSTR\ =\ 0x00U)}}
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\DoxyCodeLine{04880\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_GPIOB\_RELEASE\_RESET()\ \ \ \ \ \ \ \ \ \ \ (RCC-\/>AHB4RSTR)\ \&=\ \string~\ (RCC\_AHB4RSTR\_GPIOBRST)}}
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\DoxyCodeLine{04983\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_TIM2\_RELEASE\_RESET()\ \ \ \ \ \ \ \ \ \ \ (RCC-\/>APB1LRSTR)\ \&=\ \string~\ (RCC\_APB1LRSTR\_TIM2RST)}}
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\DoxyCodeLine{04987\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_TIM6\_RELEASE\_RESET()\ \ \ \ \ \ \ \ \ \ \ (RCC-\/>APB1LRSTR)\ \&=\ \string~\ (RCC\_APB1LRSTR\_TIM6RST)}}
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\DoxyCodeLine{04991\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_TIM14\_RELEASE\_RESET()\ \ \ \ \ \ \ \ \ \ (RCC-\/>APB1LRSTR)\ \&=\ \string~\ (RCC\_APB1LRSTR\_TIM14RST)}}
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\DoxyCodeLine{05087\ }
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\DoxyCodeLine{05866\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_TIM2\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC-\/>APB1LLPENR)\ \&=\ \string~\ (RCC\_APB1LLPENR\_TIM2LPEN)}}
\DoxyCodeLine{05867\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_TIM3\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC-\/>APB1LLPENR)\ \&=\ \string~\ (RCC\_APB1LLPENR\_TIM3LPEN)}}
\DoxyCodeLine{05868\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_TIM4\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC-\/>APB1LLPENR)\ \&=\ \string~\ (RCC\_APB1LLPENR\_TIM4LPEN)}}
\DoxyCodeLine{05869\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_TIM5\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC-\/>APB1LLPENR)\ \&=\ \string~\ (RCC\_APB1LLPENR\_TIM5LPEN)}}
\DoxyCodeLine{05870\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_TIM6\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC-\/>APB1LLPENR)\ \&=\ \string~\ (RCC\_APB1LLPENR\_TIM6LPEN)}}
\DoxyCodeLine{05871\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_TIM7\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC-\/>APB1LLPENR)\ \&=\ \string~\ (RCC\_APB1LLPENR\_TIM7LPEN)}}
\DoxyCodeLine{05872\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_TIM12\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ (RCC-\/>APB1LLPENR)\ \&=\ \string~\ (RCC\_APB1LLPENR\_TIM12LPEN)}}
\DoxyCodeLine{05873\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_TIM13\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ (RCC-\/>APB1LLPENR)\ \&=\ \string~\ (RCC\_APB1LLPENR\_TIM13LPEN)}}
\DoxyCodeLine{05874\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_TIM14\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ (RCC-\/>APB1LLPENR)\ \&=\ \string~\ (RCC\_APB1LLPENR\_TIM14LPEN)}}
\DoxyCodeLine{05875\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_LPTIM1\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ (RCC-\/>APB1LLPENR)\ \&=\ \string~\ (RCC\_APB1LLPENR\_LPTIM1LPEN)}}
\DoxyCodeLine{05876\ }
\DoxyCodeLine{05877\ \textcolor{preprocessor}{\#if\ defined(DUAL\_CORE)}}
\DoxyCodeLine{05878\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_WWDG2\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ (RCC-\/>APB1LLPENR)\ \&=\ \string~\ (RCC\_APB1LLPENR\_WWDG2LPEN)}}
\DoxyCodeLine{05879\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*DUAL\_CORE*/}\textcolor{preprocessor}{}}
\DoxyCodeLine{05880\ }
\DoxyCodeLine{05881\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_SPI2\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC-\/>APB1LLPENR)\ \&=\ \string~\ (RCC\_APB1LLPENR\_SPI2LPEN)}}
\DoxyCodeLine{05882\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_SPI3\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC-\/>APB1LLPENR)\ \&=\ \string~\ (RCC\_APB1LLPENR\_SPI3LPEN)}}
\DoxyCodeLine{05883\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_SPDIFRX\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ (RCC-\/>APB1LLPENR)\ \&=\ \string~\ (RCC\_APB1LLPENR\_SPDIFRXLPEN)}}
\DoxyCodeLine{05884\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_USART2\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ (RCC-\/>APB1LLPENR)\ \&=\ \string~\ (RCC\_APB1LLPENR\_USART2LPEN)}}
\DoxyCodeLine{05885\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_USART3\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ (RCC-\/>APB1LLPENR)\ \&=\ \string~\ (RCC\_APB1LLPENR\_USART3LPEN)}}
\DoxyCodeLine{05886\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_UART4\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ (RCC-\/>APB1LLPENR)\ \&=\ \string~\ (RCC\_APB1LLPENR\_UART4LPEN)}}
\DoxyCodeLine{05887\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_UART5\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ (RCC-\/>APB1LLPENR)\ \&=\ \string~\ (RCC\_APB1LLPENR\_UART5LPEN)}}
\DoxyCodeLine{05888\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_I2C1\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC-\/>APB1LLPENR)\ \&=\ \string~\ (RCC\_APB1LLPENR\_I2C1LPEN)}}
\DoxyCodeLine{05889\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_I2C2\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC-\/>APB1LLPENR)\ \&=\ \string~\ (RCC\_APB1LLPENR\_I2C2LPEN)}}
\DoxyCodeLine{05890\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_I2C3\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC-\/>APB1LLPENR)\ \&=\ \string~\ (RCC\_APB1LLPENR\_I2C3LPEN)}}
\DoxyCodeLine{05891\ \textcolor{preprocessor}{\#if\ defined(I2C5)}}
\DoxyCodeLine{05892\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_I2C5\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC-\/>APB1LLPENR)\ \&=\ \string~\ (RCC\_APB1LLPENR\_I2C5LPEN)}}
\DoxyCodeLine{05893\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ I2C5\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{05894\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_CEC\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ \ (RCC-\/>APB1LLPENR)\ \&=\ \string~\ (RCC\_APB1LLPENR\_CECLPEN)}}
\DoxyCodeLine{05895\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_DAC12\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ (RCC-\/>APB1LLPENR)\ \&=\ \string~\ (RCC\_APB1LLPENR\_DAC12LPEN)}}
\DoxyCodeLine{05896\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_UART7\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ (RCC-\/>APB1LLPENR)\ \&=\ \string~\ (RCC\_APB1LLPENR\_UART7LPEN)}}
\DoxyCodeLine{05897\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_UART8\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ (RCC-\/>APB1LLPENR)\ \&=\ \string~\ (RCC\_APB1LLPENR\_UART8LPEN)}}
\DoxyCodeLine{05898\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_CRS\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ \ (RCC-\/>APB1HLPENR)\ \&=\ \string~\ (RCC\_APB1HLPENR\_CRSLPEN)}}
\DoxyCodeLine{05899\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_SWPMI1\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ (RCC-\/>APB1HLPENR)\ \&=\ \string~\ (RCC\_APB1HLPENR\_SWPMILPEN)}}
\DoxyCodeLine{05900\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_OPAMP\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ (RCC-\/>APB1HLPENR)\ \&=\ \string~\ (RCC\_APB1HLPENR\_OPAMPLPEN)}}
\DoxyCodeLine{05901\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_MDIOS\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ (RCC-\/>APB1HLPENR)\ \&=\ \string~\ (RCC\_APB1HLPENR\_MDIOSLPEN)}}
\DoxyCodeLine{05902\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_FDCAN\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ (RCC-\/>APB1HLPENR)\ \&=\ \string~\ (RCC\_APB1HLPENR\_FDCANLPEN)}}
\DoxyCodeLine{05903\ \textcolor{preprocessor}{\#if\ defined(TIM23)}}
\DoxyCodeLine{05904\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_TIM23\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ (RCC-\/>APB1HLPENR)\ \&=\ \string~\ (RCC\_APB1HLPENR\_TIM23LPEN)}}
\DoxyCodeLine{05905\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ TIM23\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{05906\ \textcolor{preprocessor}{\#if\ defined(TIM24)}}
\DoxyCodeLine{05907\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_TIM24\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ (RCC-\/>APB1HLPENR)\ \&=\ \string~\ (RCC\_APB1HLPENR\_TIM24LPEN)}}
\DoxyCodeLine{05908\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ TIM24\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{05909\ }
\DoxyCodeLine{05910\ }
\DoxyCodeLine{05917\ }
\DoxyCodeLine{05918\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_TIM2\_IS\_CLK\_SLEEP\_ENABLED()\ \ \ \ \ \ \ \ \ \ \ \ ((RCC-\/>APB1LLPENR\ \&\ (RCC\_APB1LLPENR\_TIM2LPEN))\ \ \ \ !=\ 0U)}}
\DoxyCodeLine{05919\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_TIM3\_IS\_CLK\_SLEEP\_ENABLED()\ \ \ \ \ \ \ \ \ \ \ \ ((RCC-\/>APB1LLPENR\ \&\ (RCC\_APB1LLPENR\_TIM3LPEN))\ \ \ \ !=\ 0U)}}
\DoxyCodeLine{05920\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_TIM4\_IS\_CLK\_SLEEP\_ENABLED()\ \ \ \ \ \ \ \ \ \ \ \ ((RCC-\/>APB1LLPENR\ \&\ (RCC\_APB1LLPENR\_TIM4LPEN))\ \ \ \ !=\ 0U)}}
\DoxyCodeLine{05921\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_TIM5\_IS\_CLK\_SLEEP\_ENABLED()\ \ \ \ \ \ \ \ \ \ \ \ ((RCC-\/>APB1LLPENR\ \&\ (RCC\_APB1LLPENR\_TIM5LPEN))\ \ \ \ !=\ 0U)}}
\DoxyCodeLine{05922\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_TIM6\_IS\_CLK\_SLEEP\_ENABLED()\ \ \ \ \ \ \ \ \ \ \ \ ((RCC-\/>APB1LLPENR\ \&\ (RCC\_APB1LLPENR\_TIM6LPEN))\ \ \ \ !=\ 0U)}}
\DoxyCodeLine{05923\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_TIM7\_IS\_CLK\_SLEEP\_ENABLED()\ \ \ \ \ \ \ \ \ \ \ \ ((RCC-\/>APB1LLPENR\ \&\ (RCC\_APB1LLPENR\_TIM7LPEN))\ \ \ \ !=\ 0U)}}
\DoxyCodeLine{05924\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_TIM12\_IS\_CLK\_SLEEP\_ENABLED()\ \ \ \ \ \ \ \ \ \ \ ((RCC-\/>APB1LLPENR\ \&\ (RCC\_APB1LLPENR\_TIM12LPEN))\ \ \ !=\ 0U)}}
\DoxyCodeLine{05925\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_TIM13\_IS\_CLK\_SLEEP\_ENABLED()\ \ \ \ \ \ \ \ \ \ \ ((RCC-\/>APB1LLPENR\ \&\ (RCC\_APB1LLPENR\_TIM13LPEN))\ \ \ !=\ 0U)}}
\DoxyCodeLine{05926\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_TIM14\_IS\_CLK\_SLEEP\_ENABLED()\ \ \ \ \ \ \ \ \ \ \ ((RCC-\/>APB1LLPENR\ \&\ (RCC\_APB1LLPENR\_TIM14LPEN))\ \ \ !=\ 0U)}}
\DoxyCodeLine{05927\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_LPTIM1\_IS\_CLK\_SLEEP\_ENABLED()\ \ \ \ \ \ \ \ \ \ ((RCC-\/>APB1LLPENR\ \&\ (RCC\_APB1LLPENR\_LPTIM1LPEN))\ \ !=\ 0U)}}
\DoxyCodeLine{05928\ \textcolor{preprocessor}{\#if\ defined(DUAL\_CORE)}}
\DoxyCodeLine{05929\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_WWDG2\_IS\_CLK\_SLEEP\_ENABLED()\ \ \ \ \ \ \ \ \ \ \ ((RCC-\/>APB1LLPENR\ \&\ (RCC\_APB1LLPENR\_WWDG2LPEN))\ \ \ !=\ 0U)}}
\DoxyCodeLine{05930\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*DUAL\_CORE*/}\textcolor{preprocessor}{}}
\DoxyCodeLine{05931\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_SPI2\_IS\_CLK\_SLEEP\_ENABLED()\ \ \ \ \ \ \ \ \ \ \ \ ((RCC-\/>APB1LLPENR\ \&\ (RCC\_APB1LLPENR\_SPI2LPEN))\ \ \ \ !=\ 0U)}}
\DoxyCodeLine{05932\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_SPI3\_IS\_CLK\_SLEEP\_ENABLED()\ \ \ \ \ \ \ \ \ \ \ \ ((RCC-\/>APB1LLPENR\ \&\ (RCC\_APB1LLPENR\_SPI3LPEN))\ \ \ \ !=\ 0U)}}
\DoxyCodeLine{05933\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_SPDIFRX\_IS\_CLK\_SLEEP\_ENABLED()\ \ \ \ \ \ \ \ \ ((RCC-\/>APB1LLPENR\ \&\ (RCC\_APB1LLPENR\_SPDIFRXLPEN))\ !=\ 0U)}}
\DoxyCodeLine{05934\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_USART2\_IS\_CLK\_SLEEP\_ENABLED()\ \ \ \ \ \ \ \ \ \ ((RCC-\/>APB1LLPENR\ \&\ (RCC\_APB1LLPENR\_USART2LPEN))\ \ !=\ 0U)}}
\DoxyCodeLine{05935\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_USART3\_IS\_CLK\_SLEEP\_ENABLED()\ \ \ \ \ \ \ \ \ \ ((RCC-\/>APB1LLPENR\ \&\ (RCC\_APB1LLPENR\_USART3LPEN))\ \ !=\ 0U)}}
\DoxyCodeLine{05936\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_UART4\_IS\_CLK\_SLEEP\_ENABLED()\ \ \ \ \ \ \ \ \ \ \ ((RCC-\/>APB1LLPENR\ \&\ (RCC\_APB1LLPENR\_UART4LPEN))\ \ \ !=\ 0U)}}
\DoxyCodeLine{05937\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_UART5\_IS\_CLK\_SLEEP\_ENABLED()\ \ \ \ \ \ \ \ \ \ \ ((RCC-\/>APB1LLPENR\ \&\ (RCC\_APB1LLPENR\_UART5LPEN))\ \ \ !=\ 0U)}}
\DoxyCodeLine{05938\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_I2C1\_IS\_CLK\_SLEEP\_ENABLED()\ \ \ \ \ \ \ \ \ \ \ \ ((RCC-\/>APB1LLPENR\ \&\ (RCC\_APB1LLPENR\_I2C1LPEN))\ \ \ \ !=\ 0U)}}
\DoxyCodeLine{05939\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_I2C2\_IS\_CLK\_SLEEP\_ENABLED()\ \ \ \ \ \ \ \ \ \ \ \ ((RCC-\/>APB1LLPENR\ \&\ (RCC\_APB1LLPENR\_I2C2LPEN))\ \ \ \ !=\ 0U)}}
\DoxyCodeLine{05940\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_I2C3\_IS\_CLK\_SLEEP\_ENABLED()\ \ \ \ \ \ \ \ \ \ \ \ ((RCC-\/>APB1LLPENR\ \&\ (RCC\_APB1LLPENR\_I2C3LPEN))\ \ \ \ !=\ 0U)}}
\DoxyCodeLine{05941\ \textcolor{preprocessor}{\#if\ defined(I2C5)}}
\DoxyCodeLine{05942\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_I2C5\_IS\_CLK\_SLEEP\_ENABLED()\ \ \ \ \ \ \ \ \ \ \ \ ((RCC-\/>APB1LLPENR\ \&\ (RCC\_APB1LLPENR\_I2C5LPEN))\ \ \ \ !=\ 0U)}}
\DoxyCodeLine{05943\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ I2C5\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{05944\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_CEC\_IS\_CLK\_SLEEP\_ENABLED()\ \ \ \ \ \ \ \ \ \ \ \ \ ((RCC-\/>APB1LLPENR\ \&\ (RCC\_APB1LLPENR\_CECLPEN))\ \ \ \ \ !=\ 0U)}}
\DoxyCodeLine{05945\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_DAC12\_IS\_CLK\_SLEEP\_ENABLED()\ \ \ \ \ \ \ \ \ \ \ ((RCC-\/>APB1LLPENR\ \&\ (RCC\_APB1LLPENR\_DAC12LPEN))\ \ \ !=\ 0U)}}
\DoxyCodeLine{05946\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_UART7\_IS\_CLK\_SLEEP\_ENABLED()\ \ \ \ \ \ \ \ \ \ \ ((RCC-\/>APB1LLPENR\ \&\ (RCC\_APB1LLPENR\_UART7LPEN))\ \ \ !=\ 0U)}}
\DoxyCodeLine{05947\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_UART8\_IS\_CLK\_SLEEP\_ENABLED()\ \ \ \ \ \ \ \ \ \ \ ((RCC-\/>APB1LLPENR\ \&\ (RCC\_APB1LLPENR\_UART8LPEN))\ \ \ !=\ 0U)}}
\DoxyCodeLine{05948\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_CRS\_IS\_CLK\_SLEEP\_ENABLED()\ \ \ \ \ \ \ \ \ \ \ \ \ ((RCC-\/>APB1HLPENR\ \&\ (RCC\_APB1HLPENR\_CRSLPEN))\ \ \ \ \ !=\ 0U)}}
\DoxyCodeLine{05949\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_SWPMI1\_IS\_CLK\_SLEEP\_ENABLED()\ \ \ \ \ \ \ \ \ \ ((RCC-\/>APB1HLPENR\ \&\ (RCC\_APB1HLPENR\_SWPMILPEN))\ \ \ !=\ 0U)}}
\DoxyCodeLine{05950\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_OPAMP\_IS\_CLK\_SLEEP\_ENABLED()\ \ \ \ \ \ \ \ \ \ \ ((RCC-\/>APB1HLPENR\ \&\ (RCC\_APB1HLPENR\_OPAMPLPEN))\ \ \ !=\ 0U)}}
\DoxyCodeLine{05951\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_MDIOS\_IS\_CLK\_SLEEP\_ENABLED()\ \ \ \ \ \ \ \ \ \ \ ((RCC-\/>APB1HLPENR\ \&\ (RCC\_APB1HLPENR\_MDIOSLPEN))\ \ \ !=\ 0U)}}
\DoxyCodeLine{05952\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_FDCAN\_IS\_CLK\_SLEEP\_ENABLED()\ \ \ \ \ \ \ \ \ \ \ ((RCC-\/>APB1HLPENR\ \&\ (RCC\_APB1HLPENR\_FDCANLPEN))\ \ \ !=\ 0U)}}
\DoxyCodeLine{05953\ \textcolor{preprocessor}{\#if\ defined(TIM23)}}
\DoxyCodeLine{05954\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_TIM23\_IS\_CLK\_SLEEP\_ENABLED()\ \ \ \ \ \ \ \ \ \ \ ((RCC-\/>APB1HLPENR\ \&\ (RCC\_APB1HLPENR\_TIM23LPEN))\ \ \ !=\ 0U)}}
\DoxyCodeLine{05955\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ TIM23\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{05956\ \textcolor{preprocessor}{\#if\ defined(TIM24)}}
\DoxyCodeLine{05957\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_TIM24\_IS\_CLK\_SLEEP\_ENABLED()\ \ \ \ \ \ \ \ \ \ \ ((RCC-\/>APB1HLPENR\ \&\ (RCC\_APB1HLPENR\_TIM24LPEN))\ \ \ !=\ 0U)}}
\DoxyCodeLine{05958\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ TIM24\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{05959\ }
\DoxyCodeLine{05960\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_TIM2\_IS\_CLK\_SLEEP\_DISABLED()\ \ \ \ \ \ \ \ \ \ \ ((RCC-\/>APB1LLPENR\ \&\ (RCC\_APB1LLPENR\_TIM2LPEN))\ \ \ \ ==\ 0U)}}
\DoxyCodeLine{05961\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_TIM3\_IS\_CLK\_SLEEP\_DISABLED()\ \ \ \ \ \ \ \ \ \ \ ((RCC-\/>APB1LLPENR\ \&\ (RCC\_APB1LLPENR\_TIM3LPEN))\ \ \ \ ==\ 0U)}}
\DoxyCodeLine{05962\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_TIM4\_IS\_CLK\_SLEEP\_DISABLED()\ \ \ \ \ \ \ \ \ \ \ ((RCC-\/>APB1LLPENR\ \&\ (RCC\_APB1LLPENR\_TIM4LPEN))\ \ \ \ ==\ 0U)}}
\DoxyCodeLine{05963\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_TIM5\_IS\_CLK\_SLEEP\_DISABLED()\ \ \ \ \ \ \ \ \ \ \ ((RCC-\/>APB1LLPENR\ \&\ (RCC\_APB1LLPENR\_TIM5LPEN))\ \ \ \ ==\ 0U)}}
\DoxyCodeLine{05964\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_TIM6\_IS\_CLK\_SLEEP\_DISABLED()\ \ \ \ \ \ \ \ \ \ \ ((RCC-\/>APB1LLPENR\ \&\ (RCC\_APB1LLPENR\_TIM6LPEN))\ \ \ \ ==\ 0U)}}
\DoxyCodeLine{05965\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_TIM7\_IS\_CLK\_SLEEP\_DISABLED()\ \ \ \ \ \ \ \ \ \ \ ((RCC-\/>APB1LLPENR\ \&\ (RCC\_APB1LLPENR\_TIM7LPEN))\ \ \ \ ==\ 0U)}}
\DoxyCodeLine{05966\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_TIM12\_IS\_CLK\_SLEEP\_DISABLED()\ \ \ \ \ \ \ \ \ \ ((RCC-\/>APB1LLPENR\ \&\ (RCC\_APB1LLPENR\_TIM12LPEN))\ \ \ ==\ 0U)}}
\DoxyCodeLine{05967\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_TIM13\_IS\_CLK\_SLEEP\_DISABLED()\ \ \ \ \ \ \ \ \ \ ((RCC-\/>APB1LLPENR\ \&\ (RCC\_APB1LLPENR\_TIM13LPEN))\ \ \ ==\ 0U)}}
\DoxyCodeLine{05968\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_TIM14\_IS\_CLK\_SLEEP\_DISABLED()\ \ \ \ \ \ \ \ \ \ ((RCC-\/>APB1LLPENR\ \&\ (RCC\_APB1LLPENR\_TIM14LPEN))\ \ \ ==\ 0U)}}
\DoxyCodeLine{05969\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_LPTIM1\_IS\_CLK\_SLEEP\_DISABLED()\ \ \ \ \ \ \ \ \ ((RCC-\/>APB1LLPENR\ \&\ (RCC\_APB1LLPENR\_LPTIM1LPEN))\ \ ==\ 0U)}}
\DoxyCodeLine{05970\ \textcolor{preprocessor}{\#if\ defined(DUAL\_CORE)}}
\DoxyCodeLine{05971\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_WWDG2\_IS\_CLK\_SLEEP\_DISABLED()\ \ \ \ \ \ \ \ \ \ ((RCC-\/>APB1LLPENR\ \&\ (RCC\_APB1LLPENR\_WWDG2LPEN))\ \ \ ==\ 0U)}}
\DoxyCodeLine{05972\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*DUAL\_CORE*/}\textcolor{preprocessor}{}}
\DoxyCodeLine{05973\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_SPI2\_IS\_CLK\_SLEEP\_DISABLED()\ \ \ \ \ \ \ \ \ \ \ ((RCC-\/>APB1LLPENR\ \&\ (RCC\_APB1LLPENR\_SPI2LPEN))\ \ \ \ ==\ 0U)}}
\DoxyCodeLine{05974\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_SPI3\_IS\_CLK\_SLEEP\_DISABLED()\ \ \ \ \ \ \ \ \ \ \ ((RCC-\/>APB1LLPENR\ \&\ (RCC\_APB1LLPENR\_SPI3LPEN))\ \ \ \ ==\ 0U)}}
\DoxyCodeLine{05975\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_SPDIFRX\_IS\_CLK\_SLEEP\_DISABLED()\ \ \ \ \ \ \ \ ((RCC-\/>APB1LLPENR\ \&\ (RCC\_APB1LLPENR\_SPDIFRXLPEN))\ ==\ 0U)}}
\DoxyCodeLine{05976\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_USART2\_IS\_CLK\_SLEEP\_DISABLED()\ \ \ \ \ \ \ \ \ ((RCC-\/>APB1LLPENR\ \&\ (RCC\_APB1LLPENR\_USART2LPEN))\ \ ==\ 0U)}}
\DoxyCodeLine{05977\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_USART3\_IS\_CLK\_SLEEP\_DISABLED()\ \ \ \ \ \ \ \ \ ((RCC-\/>APB1LLPENR\ \&\ (RCC\_APB1LLPENR\_USART3LPEN))\ \ ==\ 0U)}}
\DoxyCodeLine{05978\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_UART4\_IS\_CLK\_SLEEP\_DISABLED()\ \ \ \ \ \ \ \ \ \ ((RCC-\/>APB1LLPENR\ \&\ (RCC\_APB1LLPENR\_UART4LPEN))\ \ \ ==\ 0U)}}
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\DoxyCodeLine{06267\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_DMA2D\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>AHB3LPENR\ |=\ (RCC\_AHB3LPENR\_DMA2DLPEN))}}
\DoxyCodeLine{06268\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_JPGDEC\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>AHB3LPENR\ |=\ (RCC\_AHB3LPENR\_JPGDECLPEN))}}
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\DoxyCodeLine{06311\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_DMA1\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>AHB1LPENR\ \&=\ \string~\ (RCC\_AHB1LPENR\_DMA1LPEN))}}
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\DoxyCodeLine{06392\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_ADC3\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>AHB4LPENR)\ \&=\ \string~\ (RCC\_AHB4LPENR\_ADC3LPEN)}}
\DoxyCodeLine{06393\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_BKPRAM\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>AHB4LPENR)\ \&=\ \string~\ (RCC\_AHB4LPENR\_BKPRAMLPEN)}}
\DoxyCodeLine{06394\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_D3SRAM1\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ (RCC\_C1-\/>AHB4LPENR\ \ \&=\ \string~\ (RCC\_AHB4LPENR\_D3SRAM1LPEN))}}
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\DoxyCodeLine{06403\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_LTDC\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB3LPENR)\ |=\ (RCC\_APB3LPENR\_LTDCLPEN)}}
\DoxyCodeLine{06404\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_DSI\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB3LPENR)\ |=\ (RCC\_APB3LPENR\_DSILPEN)}}
\DoxyCodeLine{06405\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_WWDG1\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB3LPENR)\ |=\ (RCC\_APB3LPENR\_WWDG1LPEN)}}
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\DoxyCodeLine{06407\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_LTDC\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB3LPENR)\ \&=\ \string~\ (RCC\_APB3LPENR\_LTDCLPEN)}}
\DoxyCodeLine{06408\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_DSI\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB3LPENR)\ \&=\ \string~\ (RCC\_APB3LPENR\_DSILPEN)}}
\DoxyCodeLine{06409\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_WWDG1\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB3LPENR)\ \&=\ \string~\ (RCC\_APB3LPENR\_WWDG1LPEN)}}
\DoxyCodeLine{06410\ }
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\DoxyCodeLine{06418\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_TIM2\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB1LLPENR)\ |=\ (RCC\_APB1LLPENR\_TIM2LPEN)}}
\DoxyCodeLine{06419\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_TIM3\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB1LLPENR)\ |=\ (RCC\_APB1LLPENR\_TIM3LPEN)}}
\DoxyCodeLine{06420\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_TIM4\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB1LLPENR)\ |=\ (RCC\_APB1LLPENR\_TIM4LPEN)}}
\DoxyCodeLine{06421\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_TIM5\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB1LLPENR)\ |=\ (RCC\_APB1LLPENR\_TIM5LPEN)}}
\DoxyCodeLine{06422\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_TIM6\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB1LLPENR)\ |=\ (RCC\_APB1LLPENR\_TIM6LPEN)}}
\DoxyCodeLine{06423\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_TIM7\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB1LLPENR)\ |=\ (RCC\_APB1LLPENR\_TIM7LPEN)}}
\DoxyCodeLine{06424\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_TIM12\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB1LLPENR)\ |=\ (RCC\_APB1LLPENR\_TIM12LPEN)}}
\DoxyCodeLine{06425\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_TIM13\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB1LLPENR)\ |=\ (RCC\_APB1LLPENR\_TIM13LPEN)}}
\DoxyCodeLine{06426\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_TIM14\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB1LLPENR)\ |=\ (RCC\_APB1LLPENR\_TIM14LPEN)}}
\DoxyCodeLine{06427\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_LPTIM1\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB1LLPENR)\ |=\ (RCC\_APB1LLPENR\_LPTIM1LPEN)}}
\DoxyCodeLine{06428\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_WWDG2\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB1LLPENR)\ |=\ (RCC\_APB1LLPENR\_WWDG2LPEN)}}
\DoxyCodeLine{06429\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_SPI2\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB1LLPENR)\ |=\ (RCC\_APB1LLPENR\_SPI2LPEN)}}
\DoxyCodeLine{06430\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_SPI3\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB1LLPENR)\ |=\ (RCC\_APB1LLPENR\_SPI3LPEN)}}
\DoxyCodeLine{06431\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_SPDIFRX\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ (RCC\_C1-\/>APB1LLPENR)\ |=\ (RCC\_APB1LLPENR\_SPDIFRXLPEN)}}
\DoxyCodeLine{06432\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_USART2\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB1LLPENR)\ |=\ (RCC\_APB1LLPENR\_USART2LPEN)}}
\DoxyCodeLine{06433\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_USART3\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB1LLPENR)\ |=\ (RCC\_APB1LLPENR\_USART3LPEN)}}
\DoxyCodeLine{06434\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_UART4\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB1LLPENR)\ |=\ (RCC\_APB1LLPENR\_UART4LPEN)}}
\DoxyCodeLine{06435\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_UART5\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB1LLPENR)\ |=\ (RCC\_APB1LLPENR\_UART5LPEN)}}
\DoxyCodeLine{06436\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_I2C1\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB1LLPENR)\ |=\ (RCC\_APB1LLPENR\_I2C1LPEN)}}
\DoxyCodeLine{06437\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_I2C2\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB1LLPENR)\ |=\ (RCC\_APB1LLPENR\_I2C2LPEN)}}
\DoxyCodeLine{06438\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_I2C3\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB1LLPENR)\ |=\ (RCC\_APB1LLPENR\_I2C3LPEN)}}
\DoxyCodeLine{06439\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_CEC\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB1LLPENR)\ |=\ (RCC\_APB1LLPENR\_CECLPEN)}}
\DoxyCodeLine{06440\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_DAC12\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB1LLPENR)\ |=\ (RCC\_APB1LLPENR\_DAC12LPEN)}}
\DoxyCodeLine{06441\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_UART7\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB1LLPENR)\ |=\ (RCC\_APB1LLPENR\_UART7LPEN)}}
\DoxyCodeLine{06442\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_UART8\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB1LLPENR)\ |=\ (RCC\_APB1LLPENR\_UART8LPEN)}}
\DoxyCodeLine{06443\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_CRS\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB1HLPENR)\ |=\ (RCC\_APB1HLPENR\_CRSLPEN)}}
\DoxyCodeLine{06444\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_SWPMI\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB1HLPENR)\ |=\ (RCC\_APB1HLPENR\_SWPMILPEN)}}
\DoxyCodeLine{06445\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_OPAMP\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB1HLPENR)\ |=\ (RCC\_APB1HLPENR\_OPAMPLPEN)}}
\DoxyCodeLine{06446\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_MDIOS\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB1HLPENR)\ |=\ (RCC\_APB1HLPENR\_MDIOSLPEN)}}
\DoxyCodeLine{06447\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_FDCAN\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB1HLPENR)\ |=\ (RCC\_APB1HLPENR\_FDCANLPEN)}}
\DoxyCodeLine{06448\ }
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\DoxyCodeLine{06450\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_TIM2\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB1LLPENR)\ \&=\ \string~\ (RCC\_APB1LLPENR\_TIM2LPEN)}}
\DoxyCodeLine{06451\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_TIM3\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB1LLPENR)\ \&=\ \string~\ (RCC\_APB1LLPENR\_TIM3LPEN)}}
\DoxyCodeLine{06452\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_TIM4\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB1LLPENR)\ \&=\ \string~\ (RCC\_APB1LLPENR\_TIM4LPEN)}}
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\DoxyCodeLine{06455\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_TIM7\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB1LLPENR)\ \&=\ \string~\ (RCC\_APB1LLPENR\_TIM7LPEN)}}
\DoxyCodeLine{06456\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_TIM12\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB1LLPENR)\ \&=\ \string~\ (RCC\_APB1LLPENR\_TIM12LPEN)}}
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\DoxyCodeLine{06458\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_TIM14\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB1LLPENR)\ \&=\ \string~\ (RCC\_APB1LLPENR\_TIM14LPEN)}}
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\DoxyCodeLine{06461\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_SPI2\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB1LLPENR)\ \&=\ \string~\ (RCC\_APB1LLPENR\_SPI2LPEN)}}
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\DoxyCodeLine{06466\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_UART4\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB1LLPENR)\ \&=\ \string~\ (RCC\_APB1LLPENR\_UART4LPEN)}}
\DoxyCodeLine{06467\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_UART5\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB1LLPENR)\ \&=\ \string~\ (RCC\_APB1LLPENR\_UART5LPEN)}}
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\DoxyCodeLine{06469\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_I2C2\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB1LLPENR)\ \&=\ \string~\ (RCC\_APB1LLPENR\_I2C2LPEN)}}
\DoxyCodeLine{06470\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_I2C3\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB1LLPENR)\ \&=\ \string~\ (RCC\_APB1LLPENR\_I2C3LPEN)}}
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\DoxyCodeLine{06478\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_MDIOS\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB1HLPENR)\ \&=\ \string~\ (RCC\_APB1HLPENR\_MDIOSLPEN)}}
\DoxyCodeLine{06479\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_FDCAN\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB1HLPENR)\ \&=\ \string~\ (RCC\_APB1HLPENR\_FDCANLPEN)}}
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\DoxyCodeLine{06488\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_TIM1\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB2LPENR)\ |=\ (RCC\_APB2LPENR\_TIM1LPEN)}}
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\DoxyCodeLine{06492\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_SPI1\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB2LPENR)\ |=\ (RCC\_APB2LPENR\_SPI1LPEN)}}
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\DoxyCodeLine{06494\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_TIM15\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB2LPENR)\ |=\ (RCC\_APB2LPENR\_TIM15LPEN)}}
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\DoxyCodeLine{06496\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_TIM17\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB2LPENR)\ |=\ (RCC\_APB2LPENR\_TIM17LPEN)}}
\DoxyCodeLine{06497\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_SPI5\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB2LPENR)\ |=\ (RCC\_APB2LPENR\_SPI5LPEN)}}
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\DoxyCodeLine{06503\ }
\DoxyCodeLine{06504\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_TIM1\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB2LPENR)\ \&=\ \string~\ (RCC\_APB2LPENR\_TIM1LPEN)}}
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\DoxyCodeLine{06507\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_USART6\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB2LPENR)\ \&=\ \string~\ (RCC\_APB2LPENR\_USART6LPEN)}}
\DoxyCodeLine{06508\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_SPI1\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB2LPENR)\ \&=\ \string~\ (RCC\_APB2LPENR\_SPI1LPEN)}}
\DoxyCodeLine{06509\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_SPI4\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB2LPENR)\ \&=\ \string~\ (RCC\_APB2LPENR\_SPI4LPEN)}}
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\DoxyCodeLine{06511\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_TIM16\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB2LPENR)\ \&=\ \string~\ (RCC\_APB2LPENR\_TIM16LPEN)}}
\DoxyCodeLine{06512\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_TIM17\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB2LPENR)\ \&=\ \string~\ (RCC\_APB2LPENR\_TIM17LPEN)}}
\DoxyCodeLine{06513\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_SPI5\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB2LPENR)\ \&=\ \string~\ (RCC\_APB2LPENR\_SPI5LPEN)}}
\DoxyCodeLine{06514\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_SAI1\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB2LPENR)\ \&=\ \string~\ (RCC\_APB2LPENR\_SAI1LPEN)}}
\DoxyCodeLine{06515\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_SAI2\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB2LPENR)\ \&=\ \string~\ (RCC\_APB2LPENR\_SAI2LPEN)}}
\DoxyCodeLine{06516\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_SAI3\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB2LPENR)\ \&=\ \string~\ (RCC\_APB2LPENR\_SAI3LPEN)}}
\DoxyCodeLine{06517\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_DFSDM1\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB2LPENR)\ \&=\ \string~\ (RCC\_APB2LPENR\_DFSDM1LPEN)}}
\DoxyCodeLine{06518\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_HRTIM1\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB2LPENR)\ \&=\ \string~\ (RCC\_APB2LPENR\_HRTIMLPEN)}}
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\DoxyCodeLine{06527\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_SYSCFG\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB4LPENR)\ |=\ (RCC\_APB4LPENR\_SYSCFGLPEN)}}
\DoxyCodeLine{06528\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_LPUART1\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB4LPENR)\ |=\ (RCC\_APB4LPENR\_LPUART1LPEN)}}
\DoxyCodeLine{06529\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_SPI6\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB4LPENR)\ |=\ (RCC\_APB4LPENR\_SPI6LPEN)}}
\DoxyCodeLine{06530\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_I2C4\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB4LPENR)\ |=\ (RCC\_APB4LPENR\_I2C4LPEN)}}
\DoxyCodeLine{06531\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_LPTIM2\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB4LPENR)\ |=\ (RCC\_APB4LPENR\_LPTIM2LPEN)}}
\DoxyCodeLine{06532\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_LPTIM3\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB4LPENR)\ |=\ (RCC\_APB4LPENR\_LPTIM3LPEN)}}
\DoxyCodeLine{06533\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_LPTIM4\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB4LPENR)\ |=\ (RCC\_APB4LPENR\_LPTIM4LPEN)}}
\DoxyCodeLine{06534\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_LPTIM5\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB4LPENR)\ |=\ (RCC\_APB4LPENR\_LPTIM5LPEN)}}
\DoxyCodeLine{06535\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_COMP12\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB4LPENR)\ |=\ (RCC\_APB4LPENR\_COMP12LPEN)}}
\DoxyCodeLine{06536\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_VREF\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB4LPENR)\ |=\ (RCC\_APB4LPENR\_VREFLPEN)}}
\DoxyCodeLine{06537\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_SAI4\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB4LPENR)\ |=\ (RCC\_APB4LPENR\_SAI4LPEN)}}
\DoxyCodeLine{06538\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_RTC\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB4LPENR)\ |=\ (RCC\_APB4LPENR\_RTCAPBLPEN)}}
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\DoxyCodeLine{06541\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_SYSCFG\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB4LPENR)\ \&=\ \string~\ (RCC\_APB4LPENR\_SYSCFGLPEN)}}
\DoxyCodeLine{06542\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_LPUART1\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB4LPENR)\ \&=\ \string~\ (RCC\_APB4LPENR\_LPUART1LPEN)}}
\DoxyCodeLine{06543\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_SPI6\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB4LPENR)\ \&=\ \string~\ (RCC\_APB4LPENR\_SPI6LPEN)}}
\DoxyCodeLine{06544\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_I2C4\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB4LPENR)\ \&=\ \string~\ (RCC\_APB4LPENR\_I2C4LPEN)}}
\DoxyCodeLine{06545\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_LPTIM2\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB4LPENR)\ \&=\ \string~\ (RCC\_APB4LPENR\_LPTIM2LPEN)}}
\DoxyCodeLine{06546\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_LPTIM3\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB4LPENR)\ \&=\ \string~\ (RCC\_APB4LPENR\_LPTIM3LPEN)}}
\DoxyCodeLine{06547\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_LPTIM4\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB4LPENR)\ \&=\ \string~\ (RCC\_APB4LPENR\_LPTIM4LPEN)}}
\DoxyCodeLine{06548\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_LPTIM5\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB4LPENR)\ \&=\ \string~\ (RCC\_APB4LPENR\_LPTIM5LPEN)}}
\DoxyCodeLine{06549\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_COMP12\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB4LPENR)\ \&=\ \string~\ (RCC\_APB4LPENR\_COMP12LPEN)}}
\DoxyCodeLine{06550\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_VREF\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB4LPENR)\ \&=\ \string~\ (RCC\_APB4LPENR\_VREFLPEN)}}
\DoxyCodeLine{06551\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_SAI4\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB4LPENR)\ \&=\ \string~\ (RCC\_APB4LPENR\_SAI4LPEN)}}
\DoxyCodeLine{06552\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C1\_RTC\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ \ \ \ (RCC\_C1-\/>APB4LPENR)\ \&=\ \string~\ (RCC\_APB4LPENR\_RTCAPBLPEN)}}
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\DoxyCodeLine{06562\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_MDMA\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB3LPENR\ |=\ (RCC\_AHB3LPENR\_MDMALPEN))}}
\DoxyCodeLine{06563\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_DMA2D\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB3LPENR\ |=\ (RCC\_AHB3LPENR\_DMA2DLPEN))}}
\DoxyCodeLine{06564\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_JPGDEC\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB3LPENR\ |=\ (RCC\_AHB3LPENR\_JPGDECLPEN))}}
\DoxyCodeLine{06565\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_FLASH\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB3LPENR\ |=\ (RCC\_AHB3LPENR\_FLASHLPEN))}}
\DoxyCodeLine{06566\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_FMC\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB3LPENR\ |=\ (RCC\_AHB3LPENR\_FMCLPEN))}}
\DoxyCodeLine{06567\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_QSPI\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB3LPENR\ |=\ (RCC\_AHB3LPENR\_QSPILPEN))}}
\DoxyCodeLine{06568\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_SDMMC1\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB3LPENR\ |=\ (RCC\_AHB3LPENR\_SDMMC1LPEN))}}
\DoxyCodeLine{06569\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_DTCM1\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB3LPENR\ |=\ (RCC\_AHB3LPENR\_DTCM1LPEN))}}
\DoxyCodeLine{06570\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_DTCM2\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB3LPENR\ |=\ (RCC\_AHB3LPENR\_DTCM2LPEN))}}
\DoxyCodeLine{06571\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_ITCM\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB3LPENR\ |=\ (RCC\_AHB3LPENR\_ITCMLPEN))}}
\DoxyCodeLine{06572\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_D1SRAM1\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB3LPENR\ |=\ (RCC\_AHB3LPENR\_AXISRAMLPEN))}}
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\DoxyCodeLine{06575\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_MDMA\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB3LPENR\ \&=\ \string~\ (RCC\_AHB3LPENR\_MDMALPEN))}}
\DoxyCodeLine{06576\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_DMA2D\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB3LPENR\ \&=\ \string~\ (RCC\_AHB3LPENR\_DMA2DLPEN))}}
\DoxyCodeLine{06577\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_JPGDEC\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB3LPENR\ \&=\ \string~\ (RCC\_AHB3LPENR\_JPGDECLPEN))}}
\DoxyCodeLine{06578\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_FLASH\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB3LPENR\ \&=\ \string~\ (RCC\_AHB3LPENR\_FLASHLPEN))}}
\DoxyCodeLine{06579\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_FMC\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB3LPENR\ \&=\ \string~\ (RCC\_AHB3LPENR\_FMCLPEN))}}
\DoxyCodeLine{06580\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_QSPI\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB3LPENR\ \&=\ \string~\ (RCC\_AHB3LPENR\_QSPILPEN))}}
\DoxyCodeLine{06581\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_SDMMC1\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB3LPENR\ \&=\ \string~\ (RCC\_AHB3LPENR\_SDMMC1LPEN))}}
\DoxyCodeLine{06582\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_DTCM1\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB3LPENR\ \&=\ \string~\ (RCC\_AHB3LPENR\_DTCM1LPEN))}}
\DoxyCodeLine{06583\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_DTCM2\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB3LPENR\ \&=\ \string~\ (RCC\_AHB3LPENR\_DTCM2LPEN))}}
\DoxyCodeLine{06584\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_ITCM\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB3LPENR\ \&=\ \string~\ (RCC\_AHB3LPENR\_ITCMLPEN))}}
\DoxyCodeLine{06585\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_D1SRAM1\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB3LPENR\ \&=\ \string~\ (RCC\_AHB3LPENR\_AXISRAMLPEN))}}
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\DoxyCodeLine{06596\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_DMA1\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB1LPENR\ |=\ (RCC\_AHB1LPENR\_DMA1LPEN))}}
\DoxyCodeLine{06597\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_DMA2\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB1LPENR\ |=\ (RCC\_AHB1LPENR\_DMA2LPEN))}}
\DoxyCodeLine{06598\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_ADC12\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB1LPENR\ |=\ (RCC\_AHB1LPENR\_ADC12LPEN))}}
\DoxyCodeLine{06599\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_ETH1MAC\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB1LPENR\ |=\ (RCC\_AHB1LPENR\_ETH1MACLPEN))}}
\DoxyCodeLine{06600\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_ETH1TX\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB1LPENR\ |=\ (RCC\_AHB1LPENR\_ETH1TXLPEN))}}
\DoxyCodeLine{06601\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_ETH1RX\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB1LPENR\ |=\ (RCC\_AHB1LPENR\_ETH1RXLPEN))}}
\DoxyCodeLine{06602\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_USB1\_OTG\_HS\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ (RCC\_C2-\/>AHB1LPENR\ |=\ (RCC\_AHB1LPENR\_USB1OTGHSLPEN))}}
\DoxyCodeLine{06603\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_USB1\_OTG\_HS\_ULPI\_CLK\_SLEEP\_ENABLE()\ (RCC\_C2-\/>AHB1LPENR\ |=\ (RCC\_AHB1LPENR\_USB1OTGHSULPILPEN))}}
\DoxyCodeLine{06604\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_USB2\_OTG\_FS\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ (RCC\_C2-\/>AHB1LPENR\ |=\ (RCC\_AHB1LPENR\_USB2OTGHSLPEN))}}
\DoxyCodeLine{06605\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_USB2\_OTG\_FS\_ULPI\_CLK\_SLEEP\_ENABLE()\ (RCC\_C2-\/>AHB1LPENR\ |=\ (RCC\_AHB1LPENR\_USB2OTGHSULPILPEN))}}
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\DoxyCodeLine{06607\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_DMA1\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB1LPENR\ \&=\ \string~\ (RCC\_AHB1LPENR\_DMA1LPEN))}}
\DoxyCodeLine{06608\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_DMA2\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB1LPENR\ \&=\ \string~\ (RCC\_AHB1LPENR\_DMA2LPEN))}}
\DoxyCodeLine{06609\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_ADC12\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB1LPENR\ \&=\ \string~\ (RCC\_AHB1LPENR\_ADC12LPEN))}}
\DoxyCodeLine{06610\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_ETH1MAC\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB1LPENR\ \&=\ \string~\ (RCC\_AHB1LPENR\_ETH1MACLPEN))}}
\DoxyCodeLine{06611\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_ETH1TX\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB1LPENR\ \&=\ \string~\ (RCC\_AHB1LPENR\_ETH1TXLPEN))}}
\DoxyCodeLine{06612\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_ETH1RX\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB1LPENR\ \&=\ \string~\ (RCC\_AHB1LPENR\_ETH1RXLPEN))}}
\DoxyCodeLine{06613\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_USB1\_OTG\_HS\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ (RCC\_C2-\/>AHB1LPENR\ \&=\ \string~\ (RCC\_AHB1LPENR\_USB1OTGHSLPEN))}}
\DoxyCodeLine{06614\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_USB1\_OTG\_HS\_ULPI\_CLK\_SLEEP\_DISABLE()\ (RCC\_C2-\/>AHB1LPENR\ \&=\ \string~\ (RCC\_AHB1LPENR\_USB1OTGHSULPILPEN))}}
\DoxyCodeLine{06615\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_USB2\_OTG\_FS\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ (RCC\_C2-\/>AHB1LPENR\ \&=\ \string~\ (RCC\_AHB1LPENR\_USB2OTGHSLPEN))}}
\DoxyCodeLine{06616\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_USB2\_OTG\_FS\_ULPI\_CLK\_SLEEP\_DISABLE()\ (RCC\_C2-\/>AHB1LPENR\ \&=\ \string~\ (RCC\_AHB1LPENR\_USB2OTGHSULPILPEN))}}
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\DoxyCodeLine{06625\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_DCMI\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB2LPENR\ |=\ (RCC\_AHB2LPENR\_DCMILPEN))}}
\DoxyCodeLine{06626\ \textcolor{preprocessor}{\#if\ defined(CRYP)}}
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\DoxyCodeLine{06633\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_SDMMC2\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB2LPENR\ |=\ (RCC\_AHB2LPENR\_SDMMC2LPEN))}}
\DoxyCodeLine{06634\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_D2SRAM1\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB2LPENR\ |=\ (RCC\_AHB2LPENR\_D2SRAM1LPEN))}}
\DoxyCodeLine{06635\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_D2SRAM2\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB2LPENR\ |=\ (RCC\_AHB2LPENR\_D2SRAM2LPEN))}}
\DoxyCodeLine{06636\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_D2SRAM3\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB2LPENR\ |=\ (RCC\_AHB2LPENR\_D2SRAM3LPEN))}}
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\DoxyCodeLine{06638\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_DCMI\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB2LPENR\ \&=\ \string~\ (RCC\_AHB2LPENR\_DCMILPEN))}}
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\DoxyCodeLine{06642\ \textcolor{preprocessor}{\#if\ defined(HASH)}}
\DoxyCodeLine{06643\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_HASH\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB2LPENR\ \&=\ \string~\ (RCC\_AHB2LPENR\_HASHLPEN))}}
\DoxyCodeLine{06644\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ HASH\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{06645\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_RNG\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB2LPENR\ \&=\ \string~\ (RCC\_AHB2LPENR\_RNGLPEN))}}
\DoxyCodeLine{06646\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_SDMMC2\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB2LPENR\ \&=\ \string~\ (RCC\_AHB2LPENR\_SDMMC2LPEN))}}
\DoxyCodeLine{06647\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_D2SRAM1\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB2LPENR\ \&=\ \string~\ (RCC\_AHB2LPENR\_D2SRAM1LPEN))}}
\DoxyCodeLine{06648\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_D2SRAM2\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB2LPENR\ \&=\ \string~\ (RCC\_AHB2LPENR\_D2SRAM2LPEN))}}
\DoxyCodeLine{06649\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_D2SRAM3\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB2LPENR\ \&=\ \string~\ (RCC\_AHB2LPENR\_D2SRAM3LPEN))}}
\DoxyCodeLine{06650\ }
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\DoxyCodeLine{06658\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_GPIOA\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB4LPENR)\ |=\ (RCC\_AHB4LPENR\_GPIOALPEN)}}
\DoxyCodeLine{06659\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_GPIOB\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB4LPENR)\ |=\ (RCC\_AHB4LPENR\_GPIOBLPEN)}}
\DoxyCodeLine{06660\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_GPIOC\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB4LPENR)\ |=\ (RCC\_AHB4LPENR\_GPIOCLPEN)}}
\DoxyCodeLine{06661\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_GPIOD\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB4LPENR)\ |=\ (RCC\_AHB4LPENR\_GPIODLPEN)}}
\DoxyCodeLine{06662\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_GPIOE\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB4LPENR)\ |=\ (RCC\_AHB4LPENR\_GPIOELPEN)}}
\DoxyCodeLine{06663\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_GPIOF\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB4LPENR)\ |=\ (RCC\_AHB4LPENR\_GPIOFLPEN)}}
\DoxyCodeLine{06664\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_GPIOG\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB4LPENR)\ |=\ (RCC\_AHB4LPENR\_GPIOGLPEN)}}
\DoxyCodeLine{06665\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_GPIOH\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB4LPENR)\ |=\ (RCC\_AHB4LPENR\_GPIOHLPEN)}}
\DoxyCodeLine{06666\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_GPIOI\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB4LPENR)\ |=\ (RCC\_AHB4LPENR\_GPIOILPEN)}}
\DoxyCodeLine{06667\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_GPIOJ\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB4LPENR)\ |=\ (RCC\_AHB4LPENR\_GPIOJLPEN)}}
\DoxyCodeLine{06668\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_GPIOK\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB4LPENR)\ |=\ (RCC\_AHB4LPENR\_GPIOKLPEN)}}
\DoxyCodeLine{06669\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_CRC\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB4LPENR)\ |=\ (RCC\_AHB4LPENR\_CRCLPEN)}}
\DoxyCodeLine{06670\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_BDMA\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB4LPENR)\ |=\ (RCC\_AHB4LPENR\_BDMALPEN)}}
\DoxyCodeLine{06671\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_ADC3\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB4LPENR)\ |=\ (RCC\_AHB4LPENR\_ADC3LPEN)}}
\DoxyCodeLine{06672\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_BKPRAM\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB4LPENR)\ |=\ (RCC\_AHB4LPENR\_BKPRAMLPEN)}}
\DoxyCodeLine{06673\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_D3SRAM1\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB4LPENR\ \ |=\ (RCC\_AHB4LPENR\_D3SRAM1LPEN))}}
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\DoxyCodeLine{06675\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_GPIOA\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB4LPENR)\ \&=\ \string~\ (RCC\_AHB4LPENR\_GPIOALPEN)}}
\DoxyCodeLine{06676\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_GPIOB\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB4LPENR)\ \&=\ \string~\ (RCC\_AHB4LPENR\_GPIOBLPEN)}}
\DoxyCodeLine{06677\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_GPIOC\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB4LPENR)\ \&=\ \string~\ (RCC\_AHB4LPENR\_GPIOCLPEN)}}
\DoxyCodeLine{06678\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_GPIOD\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB4LPENR)\ \&=\ \string~\ (RCC\_AHB4LPENR\_GPIODLPEN)}}
\DoxyCodeLine{06679\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_GPIOE\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB4LPENR)\ \&=\ \string~\ (RCC\_AHB4LPENR\_GPIOELPEN)}}
\DoxyCodeLine{06680\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_GPIOF\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB4LPENR)\ \&=\ \string~\ (RCC\_AHB4LPENR\_GPIOFLPEN)}}
\DoxyCodeLine{06681\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_GPIOG\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB4LPENR)\ \&=\ \string~\ (RCC\_AHB4LPENR\_GPIOGLPEN)}}
\DoxyCodeLine{06682\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_GPIOH\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB4LPENR)\ \&=\ \string~\ (RCC\_AHB4LPENR\_GPIOHLPEN)}}
\DoxyCodeLine{06683\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_GPIOI\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB4LPENR)\ \&=\ \string~\ (RCC\_AHB4LPENR\_GPIOILPEN)}}
\DoxyCodeLine{06684\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_GPIOJ\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB4LPENR)\ \&=\ \string~\ (RCC\_AHB4LPENR\_GPIOJLPEN)}}
\DoxyCodeLine{06685\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_GPIOK\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB4LPENR)\ \&=\ \string~\ (RCC\_AHB4LPENR\_GPIOKLPEN)}}
\DoxyCodeLine{06686\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_CRC\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB4LPENR)\ \&=\ \string~\ (RCC\_AHB4LPENR\_CRCLPEN)}}
\DoxyCodeLine{06687\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_BDMA\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB4LPENR)\ \&=\ \string~\ (RCC\_AHB4LPENR\_BDMALPEN)}}
\DoxyCodeLine{06688\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_ADC3\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB4LPENR)\ \&=\ \string~\ (RCC\_AHB4LPENR\_ADC3LPEN)}}
\DoxyCodeLine{06689\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_BKPRAM\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB4LPENR)\ \&=\ \string~\ (RCC\_AHB4LPENR\_BKPRAMLPEN)}}
\DoxyCodeLine{06690\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_D3SRAM1\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ (RCC\_C2-\/>AHB4LPENR\ \ \&=\ \string~\ (RCC\_AHB4LPENR\_D3SRAM1LPEN))}}
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\DoxyCodeLine{06699\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_LTDC\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>APB3LPENR)\ |=\ (RCC\_APB3LPENR\_LTDCLPEN)}}
\DoxyCodeLine{06700\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_DSI\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>APB3LPENR)\ |=\ (RCC\_APB3LPENR\_DSILPEN)}}
\DoxyCodeLine{06701\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_WWDG1\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>APB3LPENR)\ |=\ (RCC\_APB3LPENR\_WWDG1LPEN)}}
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\DoxyCodeLine{06703\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_LTDC\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>APB3LPENR)\ \&=\ \string~\ (RCC\_APB3LPENR\_LTDCLPEN)}}
\DoxyCodeLine{06704\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_DSI\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>APB3LPENR)\ \&=\ \string~\ (RCC\_APB3LPENR\_DSILPEN)}}
\DoxyCodeLine{06705\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_WWDG1\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>APB3LPENR)\ \&=\ \string~\ (RCC\_APB3LPENR\_WWDG1LPEN)}}
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\DoxyCodeLine{06714\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_TIM2\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>APB1LLPENR)\ |=\ (RCC\_APB1LLPENR\_TIM2LPEN)}}
\DoxyCodeLine{06715\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_TIM3\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>APB1LLPENR)\ |=\ (RCC\_APB1LLPENR\_TIM3LPEN)}}
\DoxyCodeLine{06716\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_TIM4\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>APB1LLPENR)\ |=\ (RCC\_APB1LLPENR\_TIM4LPEN)}}
\DoxyCodeLine{06717\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_TIM5\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>APB1LLPENR)\ |=\ (RCC\_APB1LLPENR\_TIM5LPEN)}}
\DoxyCodeLine{06718\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_TIM6\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>APB1LLPENR)\ |=\ (RCC\_APB1LLPENR\_TIM6LPEN)}}
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\DoxyCodeLine{06721\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_TIM13\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>APB1LLPENR)\ |=\ (RCC\_APB1LLPENR\_TIM13LPEN)}}
\DoxyCodeLine{06722\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_TIM14\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>APB1LLPENR)\ |=\ (RCC\_APB1LLPENR\_TIM14LPEN)}}
\DoxyCodeLine{06723\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_LPTIM1\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ (RCC\_C2-\/>APB1LLPENR)\ |=\ (RCC\_APB1LLPENR\_LPTIM1LPEN)}}
\DoxyCodeLine{06724\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_WWDG2\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>APB1LLPENR)\ |=\ (RCC\_APB1LLPENR\_WWDG2LPEN)}}
\DoxyCodeLine{06725\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_SPI2\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>APB1LLPENR)\ |=\ (RCC\_APB1LLPENR\_SPI2LPEN)}}
\DoxyCodeLine{06726\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_SPI3\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>APB1LLPENR)\ |=\ (RCC\_APB1LLPENR\_SPI3LPEN)}}
\DoxyCodeLine{06727\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_SPDIFRX\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ (RCC\_C2-\/>APB1LLPENR)\ |=\ (RCC\_APB1LLPENR\_SPDIFRXLPEN)}}
\DoxyCodeLine{06728\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_USART2\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ (RCC\_C2-\/>APB1LLPENR)\ |=\ (RCC\_APB1LLPENR\_USART2LPEN)}}
\DoxyCodeLine{06729\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_USART3\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ (RCC\_C2-\/>APB1LLPENR)\ |=\ (RCC\_APB1LLPENR\_USART3LPEN)}}
\DoxyCodeLine{06730\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_UART4\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>APB1LLPENR)\ |=\ (RCC\_APB1LLPENR\_UART4LPEN)}}
\DoxyCodeLine{06731\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_UART5\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>APB1LLPENR)\ |=\ (RCC\_APB1LLPENR\_UART5LPEN)}}
\DoxyCodeLine{06732\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_I2C1\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>APB1LLPENR)\ |=\ (RCC\_APB1LLPENR\_I2C1LPEN)}}
\DoxyCodeLine{06733\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_I2C2\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>APB1LLPENR)\ |=\ (RCC\_APB1LLPENR\_I2C2LPEN)}}
\DoxyCodeLine{06734\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_I2C3\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>APB1LLPENR)\ |=\ (RCC\_APB1LLPENR\_I2C3LPEN)}}
\DoxyCodeLine{06735\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_CEC\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>APB1LLPENR)\ |=\ (RCC\_APB1LLPENR\_CECLPEN)}}
\DoxyCodeLine{06736\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_DAC12\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>APB1LLPENR)\ |=\ (RCC\_APB1LLPENR\_DAC12LPEN)}}
\DoxyCodeLine{06737\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_UART7\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>APB1LLPENR)\ |=\ (RCC\_APB1LLPENR\_UART7LPEN)}}
\DoxyCodeLine{06738\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_UART8\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>APB1LLPENR)\ |=\ (RCC\_APB1LLPENR\_UART8LPEN)}}
\DoxyCodeLine{06739\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_CRS\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>APB1HLPENR)\ |=\ (RCC\_APB1HLPENR\_CRSLPEN)}}
\DoxyCodeLine{06740\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_SWPMI\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>APB1HLPENR)\ |=\ (RCC\_APB1HLPENR\_SWPMILPEN)}}
\DoxyCodeLine{06741\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_OPAMP\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>APB1HLPENR)\ |=\ (RCC\_APB1HLPENR\_OPAMPLPEN)}}
\DoxyCodeLine{06742\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_MDIOS\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>APB1HLPENR)\ |=\ (RCC\_APB1HLPENR\_MDIOSLPEN)}}
\DoxyCodeLine{06743\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_FDCAN\_CLK\_SLEEP\_ENABLE()\ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>APB1HLPENR)\ |=\ (RCC\_APB1HLPENR\_FDCANLPEN)}}
\DoxyCodeLine{06744\ }
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\DoxyCodeLine{06746\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_TIM2\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>APB1LLPENR)\ \&=\ \string~\ (RCC\_APB1LLPENR\_TIM2LPEN)}}
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\DoxyCodeLine{06748\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_TIM4\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>APB1LLPENR)\ \&=\ \string~\ (RCC\_APB1LLPENR\_TIM4LPEN)}}
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\DoxyCodeLine{06750\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_TIM6\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>APB1LLPENR)\ \&=\ \string~\ (RCC\_APB1LLPENR\_TIM6LPEN)}}
\DoxyCodeLine{06751\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_TIM7\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>APB1LLPENR)\ \&=\ \string~\ (RCC\_APB1LLPENR\_TIM7LPEN)}}
\DoxyCodeLine{06752\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_TIM12\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>APB1LLPENR)\ \&=\ \string~\ (RCC\_APB1LLPENR\_TIM12LPEN)}}
\DoxyCodeLine{06753\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_TIM13\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>APB1LLPENR)\ \&=\ \string~\ (RCC\_APB1LLPENR\_TIM13LPEN)}}
\DoxyCodeLine{06754\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_TIM14\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>APB1LLPENR)\ \&=\ \string~\ (RCC\_APB1LLPENR\_TIM14LPEN)}}
\DoxyCodeLine{06755\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_LPTIM1\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ (RCC\_C2-\/>APB1LLPENR)\ \&=\ \string~\ (RCC\_APB1LLPENR\_LPTIM1LPEN)}}
\DoxyCodeLine{06756\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_WWDG2\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>APB1LLPENR)\ \&=\ \string~\ (RCC\_APB1LLPENR\_WWDG2LPEN)}}
\DoxyCodeLine{06757\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_C2\_SPI2\_CLK\_SLEEP\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC\_C2-\/>APB1LLPENR)\ \&=\ \string~\ (RCC\_APB1LLPENR\_SPI2LPEN)}}
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\DoxyCodeLine{07078\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_AXIRAM3\_CLKGA\_ENABLE()\ \ \ \ \ \ \ \ \ (RCC-\/>CKGAENR)\ |=\ (RCC\_CKGAENR\_AXIRAM3CKG)}}
\DoxyCodeLine{07079\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_GFXMMUS\_CLKGA\_ENABLE()\ \ \ \ \ \ \ \ \ (RCC-\/>CKGAENR)\ |=\ (RCC\_CKGAENR\_GFXMMUSCKG)}}
\DoxyCodeLine{07080\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_ECCRAM\_CLKGA\_ENABLE()\ \ \ \ \ \ \ \ \ \ (RCC-\/>CKGAENR)\ |=\ (RCC\_CKGAENR\_ECCRAMCKG)}}
\DoxyCodeLine{07081\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_EXTI\_CLKGA\_ENABLE()\ \ \ \ \ \ \ \ \ \ \ \ (RCC-\/>CKGAENR)\ |=\ (RCC\_CKGAENR\_EXTICKG)}}
\DoxyCodeLine{07082\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_JTAG\_CLKGA\_ENABLE()\ \ \ \ \ \ \ \ \ \ \ \ (RCC-\/>CKGAENR)\ |=\ (RCC\_CKGAENR\_JTAGCKG)}}
\DoxyCodeLine{07083\ }
\DoxyCodeLine{07084\ }
\DoxyCodeLine{07085\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_AXI\_CLKGA\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ \ \ (RCC-\/>CKGAENR)\ \&=\ \string~\ (RCC\_CKGAENR\_AXICKG)}}
\DoxyCodeLine{07086\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_AHB\_CLKGA\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ \ \ (RCC-\/>CKGAENR)\ \&=\ \string~\ (RCC\_CKGAENR\_AHBCKG)}}
\DoxyCodeLine{07087\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_CPU\_CLKGA\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ \ \ (RCC-\/>CKGAENR)\ \&=\ \string~\ (RCC\_CKGAENR\_CPUCKG)}}
\DoxyCodeLine{07088\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_SDMMC\_CLKGA\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC-\/>CKGAENR)\ \&=\ \string~\ (RCC\_CKGAENR\_SDMMCCKG)}}
\DoxyCodeLine{07089\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_MDMA\_CLKGA\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ \ (RCC-\/>CKGAENR)\ \&=\ \string~\ (RCC\_CKGAENR\_MDMACKG)}}
\DoxyCodeLine{07090\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_DMA2D\_CLKGA\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC-\/>CKGAENR)\ \&=\ \string~\ (RCC\_CKGAENR\_DMA2DCKG)}}
\DoxyCodeLine{07091\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_LTDC\_CLKGA\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ \ (RCC-\/>CKGAENR)\ \&=\ \string~\ (RCC\_CKGAENR\_LTDCCKG)}}
\DoxyCodeLine{07092\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_GFXMMUM\_CLKGA\_DISABLE()\ \ \ \ \ \ \ \ \ (RCC-\/>CKGAENR)\ \&=\ \string~\ (RCC\_CKGAENR\_GFXMMUMCKG)}}
\DoxyCodeLine{07093\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_AHB12\_CLKGA\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC-\/>CKGAENR)\ \&=\ \string~\ (RCC\_CKGAENR\_AHB12CKG)}}
\DoxyCodeLine{07094\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_AHB34\_CLKGA\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC-\/>CKGAENR)\ \&=\ \string~\ (RCC\_CKGAENR\_AHB34CKG)}}
\DoxyCodeLine{07095\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_FLIFT\_CLKGA\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ (RCC-\/>CKGAENR)\ \&=\ \string~\ (RCC\_CKGAENR\_FLIFTCKG)}}
\DoxyCodeLine{07096\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_OCTOSPI2\_CLKGA\_DISABLE()\ \ \ \ \ \ \ \ (RCC-\/>CKGAENR)\ \&=\ \string~\ (RCC\_CKGAENR\_OCTOSPI2CKG)}}
\DoxyCodeLine{07097\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_FMC\_CLKGA\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ \ \ (RCC-\/>CKGAENR)\ \&=\ \string~\ (RCC\_CKGAENR\_FMCCKG)}}
\DoxyCodeLine{07098\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_OCTOSPI1\_CLKGA\_DISABLE()\ \ \ \ \ \ \ \ (RCC-\/>CKGAENR)\ \&=\ \string~\ (RCC\_CKGAENR\_OCTOSPI1CKG)}}
\DoxyCodeLine{07099\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_AXIRAM1\_CLKGA\_DISABLE()\ \ \ \ \ \ \ \ \ (RCC-\/>CKGAENR)\ \&=\ \string~\ (RCC\_CKGAENR\_AXIRAM1CKG)}}
\DoxyCodeLine{07100\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_AXIRAM2\_CLKGA\_DISABLE()\ \ \ \ \ \ \ \ \ (RCC-\/>CKGAENR)\ \&=\ \string~\ (RCC\_CKGAENR\_AXIRAM2CKG)}}
\DoxyCodeLine{07101\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_AXIRAM3\_CLKGA\_DISABLE()\ \ \ \ \ \ \ \ \ (RCC-\/>CKGAENR)\ \&=\ \string~\ (RCC\_CKGAENR\_AXIRAM3CKG)}}
\DoxyCodeLine{07102\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_GFXMMUS\_CLKGA\_DISABLE()\ \ \ \ \ \ \ \ \ (RCC-\/>CKGAENR)\ \&=\ \string~\ (RCC\_CKGAENR\_GFXMMUSCKG)}}
\DoxyCodeLine{07103\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_ECCRAM\_CLKGA\_DISABLE()\ \ \ \ \ \ \ \ \ \ (RCC-\/>CKGAENR)\ \&=\ \string~\ (RCC\_CKGAENR\_ECCRAMCKG)}}
\DoxyCodeLine{07104\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_EXTI\_CLKGA\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ \ (RCC-\/>CKGAENR)\ \&=\ \string~\ (RCC\_CKGAENR\_EXTICKG)}}
\DoxyCodeLine{07105\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_JTAG\_CLKGA\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ \ (RCC-\/>CKGAENR)\ \&=\ \string~\ (RCC\_CKGAENR\_JTAGCKG)}}
\DoxyCodeLine{07106\ }
\DoxyCodeLine{07107\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ RCC\_CKGAENR\_AXICKG\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{07108\ }
\DoxyCodeLine{07109\ }
\DoxyCodeLine{07110\ }
\DoxyCodeLine{07111\ }
\DoxyCodeLine{07131\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_HSI\_CONFIG(\_\_STATE\_\_)\ \(\backslash\)}}
\DoxyCodeLine{07132\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ MODIFY\_REG(RCC-\/>CR,\ RCC\_CR\_HSION\ |\ RCC\_CR\_HSIDIV\ ,\ (uint32\_t)(\_\_STATE\_\_))}}
\DoxyCodeLine{07133\ }
\DoxyCodeLine{07134\ }
\DoxyCodeLine{07143\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_GET\_HSI\_DIVIDER()\ ((uint32\_t)(READ\_BIT(RCC-\/>CR,\ RCC\_CR\_HSIDIV)))}}
\DoxyCodeLine{07144\ }
\DoxyCodeLine{07160\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_HSI\_ENABLE()\ \ SET\_BIT(RCC-\/>CR,\ RCC\_CR\_HSION)}}
\DoxyCodeLine{07161\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_HSI\_DISABLE()\ CLEAR\_BIT(RCC-\/>CR,\ RCC\_CR\_HSION)}}
\DoxyCodeLine{07162\ }
\DoxyCodeLine{07163\ }
\DoxyCodeLine{07170\ \textcolor{preprocessor}{\#if\ defined(RCC\_VER\_X)}}
\DoxyCodeLine{07171\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_HSI\_CALIBRATIONVALUE\_ADJUST(\_\_HSICalibrationValue\_\_)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07172\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ do\ \{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07173\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ if(HAL\_GetREVID()\ <=\ REV\_ID\_Y)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07174\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07175\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ if((\_\_HSICalibrationValue\_\_)\ ==\ RCC\_HSICALIBRATION\_DEFAULT)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07176\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07177\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ MODIFY\_REG(RCC-\/>HSICFGR,\ HAL\_RCC\_REV\_Y\_HSITRIM\_Msk,\ ((uint32\_t)0x20)\ <<\ HAL\_RCC\_REV\_Y\_HSITRIM\_Pos);\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07178\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07179\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ else\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07180\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07181\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ MODIFY\_REG(RCC-\/>HSICFGR,\ HAL\_RCC\_REV\_Y\_HSITRIM\_Msk,\ (uint32\_t)(\_\_HSICalibrationValue\_\_)\ <<\ HAL\_RCC\_REV\_Y\_HSITRIM\_Pos);\ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07182\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \}\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07183\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07184\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ else\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07185\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07186\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ MODIFY\_REG(RCC-\/>HSICFGR,\ RCC\_HSICFGR\_HSITRIM,\ (uint32\_t)(\_\_HSICalibrationValue\_\_)\ <<\ RCC\_HSICFGR\_HSITRIM\_Pos);\ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07187\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \}\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07188\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \}\ while(0)}}
\DoxyCodeLine{07189\ }
\DoxyCodeLine{07190\ \textcolor{preprocessor}{\#else}}
\DoxyCodeLine{07191\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_HSI\_CALIBRATIONVALUE\_ADJUST(\_\_HSICalibrationValue\_\_)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07192\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ MODIFY\_REG(RCC-\/>HSICFGR,\ RCC\_HSICFGR\_HSITRIM,\ (uint32\_t)(\_\_HSICalibrationValue\_\_)\ <<\ RCC\_HSICFGR\_HSITRIM\_Pos);}}
\DoxyCodeLine{07193\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*RCC\_VER\_X*/}\textcolor{preprocessor}{}\textcolor{preprocessor}{}}
\DoxyCodeLine{07203\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_HSISTOP\_ENABLE()\ \ \ \ \ SET\_BIT(RCC-\/>CR,\ RCC\_CR\_HSIKERON)}}
\DoxyCodeLine{07204\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_HSISTOP\_DISABLE()\ \ \ \ CLEAR\_BIT(RCC-\/>CR,\ RCC\_CR\_HSIKERON)}}
\DoxyCodeLine{07205\ }
\DoxyCodeLine{07206\ }
\DoxyCodeLine{07214\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_HSI48\_ENABLE()\ \ \ \ SET\_BIT(RCC-\/>CR,\ RCC\_CR\_HSI48ON);}}
\DoxyCodeLine{07215\ }
\DoxyCodeLine{07216\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_HSI48\_DISABLE()\ \ \ CLEAR\_BIT(RCC-\/>CR,\ RCC\_CR\_HSI48ON);}}
\DoxyCodeLine{07217\ }
\DoxyCodeLine{07234\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_CSI\_ENABLE()\ \ SET\_BIT(RCC-\/>CR,\ RCC\_CR\_CSION)}}
\DoxyCodeLine{07235\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_CSI\_DISABLE()\ CLEAR\_BIT(RCC-\/>CR,\ RCC\_CR\_CSION)}}
\DoxyCodeLine{07236\ }
\DoxyCodeLine{07243\ \textcolor{preprocessor}{\#if\ defined(RCC\_VER\_X)}}
\DoxyCodeLine{07244\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_CSI\_CALIBRATIONVALUE\_ADJUST(\_\_CSICalibrationValue\_\_)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07245\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ do\ \{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07246\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ if(HAL\_GetREVID()\ <=\ REV\_ID\_Y)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07247\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07248\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ if((\_\_CSICalibrationValue\_\_)\ ==\ RCC\_CSICALIBRATION\_DEFAULT)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07249\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07250\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ MODIFY\_REG(RCC-\/>HSICFGR,\ HAL\_RCC\_REV\_Y\_CSITRIM\_Msk,\ ((uint32\_t)0x10)\ <<\ HAL\_RCC\_REV\_Y\_CSITRIM\_Pos);\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07251\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07252\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ else\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07253\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07254\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ MODIFY\_REG(RCC-\/>HSICFGR,\ HAL\_RCC\_REV\_Y\_CSITRIM\_Msk,\ (uint32\_t)(\_\_CSICalibrationValue\_\_)\ <<\ HAL\_RCC\_REV\_Y\_CSITRIM\_Pos);\ \(\backslash\)}}
\DoxyCodeLine{07255\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07256\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \}\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07257\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ else\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07258\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07259\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ MODIFY\_REG(RCC-\/>CSICFGR,\ RCC\_CSICFGR\_CSITRIM,\ (uint32\_t)(\_\_CSICalibrationValue\_\_)\ <<\ RCC\_CSICFGR\_CSITRIM\_Pos);\ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07260\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \}\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07261\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \}\ while(0)}}
\DoxyCodeLine{07262\ }
\DoxyCodeLine{07263\ \textcolor{preprocessor}{\#else}}
\DoxyCodeLine{07264\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_CSI\_CALIBRATIONVALUE\_ADJUST(\_\_CSICalibrationValue\_\_)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07265\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ do\ \{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07266\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ MODIFY\_REG(RCC-\/>CSICFGR,\ RCC\_CSICFGR\_CSITRIM,\ (uint32\_t)(\_\_CSICalibrationValue\_\_)\ <<\ RCC\_CSICFGR\_CSITRIM\_Pos);\ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07267\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ while(0)}}
\DoxyCodeLine{07268\ }
\DoxyCodeLine{07269\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*RCC\_VER\_X*/}\textcolor{preprocessor}{}\textcolor{preprocessor}{}}
\DoxyCodeLine{07279\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_CSISTOP\_ENABLE()\ \ \ \ \ SET\_BIT(RCC-\/>CR,\ RCC\_CR\_CSIKERON)}}
\DoxyCodeLine{07280\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_CSISTOP\_DISABLE()\ \ \ \ CLEAR\_BIT(RCC-\/>CR,\ RCC\_CR\_CSIKERON)}}
\DoxyCodeLine{07281\ }
\DoxyCodeLine{07282\ }
\DoxyCodeLine{07291\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_LSI\_ENABLE()\ \ \ \ \ \ \ \ \ SET\_BIT(RCC-\/>CSR,\ RCC\_CSR\_LSION)}}
\DoxyCodeLine{07292\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_LSI\_DISABLE()\ \ \ \ \ \ \ \ CLEAR\_BIT(RCC-\/>CSR,\ RCC\_CSR\_LSION)}}
\DoxyCodeLine{07293\ }
\DoxyCodeLine{07316\ \textcolor{preprocessor}{\#if\ defined(RCC\_CR\_HSEEXT)}}
\DoxyCodeLine{07317\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_HSE\_CONFIG(\_\_STATE\_\_)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07318\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ do\ \{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07319\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ if\ ((\_\_STATE\_\_)\ ==\ RCC\_HSE\_ON)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07320\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07321\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC-\/>CR,\ RCC\_CR\_HSEON);\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07322\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07323\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ else\ if\ ((\_\_STATE\_\_)\ ==\ RCC\_HSE\_OFF)\ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07324\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07325\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ CLEAR\_BIT(RCC-\/>CR,\ RCC\_CR\_HSEON);\ \ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07326\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ CLEAR\_BIT(RCC-\/>CR,\ RCC\_CR\_HSEEXT);\ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07327\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ CLEAR\_BIT(RCC-\/>CR,\ RCC\_CR\_HSEBYP);\ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07328\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07329\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ else\ if\ ((\_\_STATE\_\_)\ ==\ RCC\_HSE\_BYPASS)\ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07330\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07331\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC-\/>CR,\ RCC\_CR\_HSEBYP);\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07332\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ CLEAR\_BIT(RCC-\/>CR,\ RCC\_CR\_HSEEXT);\ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07333\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC-\/>CR,\ RCC\_CR\_HSEON);\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07334\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07335\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ else\ if((\_\_STATE\_\_)\ ==\ RCC\_HSE\_BYPASS\_DIGITAL)\ \ \ \(\backslash\)}}
\DoxyCodeLine{07336\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07337\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC-\/>CR,\ RCC\_CR\_HSEBYP);\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07338\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC-\/>CR,\ RCC\_CR\_HSEEXT);\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07339\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC-\/>CR,\ RCC\_CR\_HSEON);\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07340\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07341\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ else\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07342\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07343\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ CLEAR\_BIT(RCC-\/>CR,\ RCC\_CR\_HSEON);\ \ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07344\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ CLEAR\_BIT(RCC-\/>CR,\ RCC\_CR\_HSEBYP);\ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07345\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ CLEAR\_BIT(RCC-\/>CR,\ RCC\_CR\_HSEEXT);\ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07346\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07347\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ while(0)}}
\DoxyCodeLine{07348\ \textcolor{preprocessor}{\#else}}
\DoxyCodeLine{07349\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_HSE\_CONFIG(\_\_STATE\_\_)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07350\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ do\ \{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07351\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ if\ ((\_\_STATE\_\_)\ ==\ RCC\_HSE\_ON)\ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07352\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07353\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC-\/>CR,\ RCC\_CR\_HSEON);\ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07354\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07355\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ else\ if\ ((\_\_STATE\_\_)\ ==\ RCC\_HSE\_OFF)\ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07356\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07357\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ CLEAR\_BIT(RCC-\/>CR,\ RCC\_CR\_HSEON);\ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07358\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ CLEAR\_BIT(RCC-\/>CR,\ RCC\_CR\_HSEBYP);\ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07359\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07360\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ else\ if\ ((\_\_STATE\_\_)\ ==\ RCC\_HSE\_BYPASS)\ \ \ \(\backslash\)}}
\DoxyCodeLine{07361\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07362\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC-\/>CR,\ RCC\_CR\_HSEBYP);\ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07363\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC-\/>CR,\ RCC\_CR\_HSEON);\ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07364\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07365\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ else\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07366\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07367\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ CLEAR\_BIT(RCC-\/>CR,\ RCC\_CR\_HSEON);\ \ \ \ \ \ \ \(\backslash\)}}
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\DoxyCodeLine{07369\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07370\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ while(0)}}
\DoxyCodeLine{07371\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ RCC\_CR\_HSEEXT\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{07372\ }
\DoxyCodeLine{07376\ }
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\DoxyCodeLine{07402\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_LSE\_CONFIG(\_\_STATE\_\_)\ \(\backslash\)}}
\DoxyCodeLine{07403\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ do\ \{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07404\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ if((\_\_STATE\_\_)\ ==\ RCC\_LSE\_ON)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07405\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07406\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC-\/>BDCR,\ RCC\_BDCR\_LSEON);\ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07407\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07408\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ else\ if((\_\_STATE\_\_)\ ==\ RCC\_LSE\_OFF)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07409\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07410\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ CLEAR\_BIT(RCC-\/>BDCR,\ RCC\_BDCR\_LSEON);\ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07411\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ CLEAR\_BIT(RCC-\/>BDCR,\ RCC\_BDCR\_LSEEXT);\ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07412\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ CLEAR\_BIT(RCC-\/>BDCR,\ RCC\_BDCR\_LSEBYP);\ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07413\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07414\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ else\ if((\_\_STATE\_\_)\ ==\ RCC\_LSE\_BYPASS)\ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07415\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07416\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC-\/>BDCR,\ RCC\_BDCR\_LSEBYP);\ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07417\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ CLEAR\_BIT(RCC-\/>BDCR,\ RCC\_BDCR\_LSEEXT);\ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07418\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC-\/>BDCR,\ RCC\_BDCR\_LSEON);\ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07419\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07420\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ else\ if((\_\_STATE\_\_)\ ==\ RCC\_LSE\_BYPASS\_DIGITAL)\ \ \ \(\backslash\)}}
\DoxyCodeLine{07421\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07422\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC-\/>BDCR,\ RCC\_BDCR\_LSEBYP);\ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07423\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC-\/>BDCR,\ RCC\_BDCR\_LSEEXT);\ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07424\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SET\_BIT(RCC-\/>BDCR,\ RCC\_BDCR\_LSEON);\ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07425\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07426\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ else\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07427\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07428\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ CLEAR\_BIT(RCC-\/>BDCR,\ RCC\_BDCR\_LSEON);\ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07429\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ CLEAR\_BIT(RCC-\/>BDCR,\ RCC\_BDCR\_LSEBYP);\ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07430\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ CLEAR\_BIT(RCC-\/>BDCR,\ RCC\_BDCR\_LSEEXT);\ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07431\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{07432\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ while(0)}}
\DoxyCodeLine{07433\ \textcolor{preprocessor}{\#else}}
\DoxyCodeLine{07434\ }
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\DoxyCodeLine{07944\ \textcolor{preprocessor}{((((\_\_FLAG\_\_)\ >>\ 5U)\ ==\ 3U)?\ RCC-\/>CSR\ :\ ((((\_\_FLAG\_\_)\ >>\ 5U)\ ==\ 4U)?\ RCC-\/>RSR\ :RCC-\/>CIFR))))\ \ \&\ (1UL\ <<\ ((\_\_FLAG\_\_)\ \&\ RCC\_FLAG\_MASK)))!=\ 0U)?\ 1U\ :\ 0U)}}
\DoxyCodeLine{07945\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*DUAL\_CORE*/}\textcolor{preprocessor}{}}
\DoxyCodeLine{07946\ }
\DoxyCodeLine{07950\ }
\DoxyCodeLine{07951\ \textcolor{preprocessor}{\#define\ RCC\_GET\_PLL\_OSCSOURCE()\ ((RCC-\/>PLLCKSELR\ \&\ RCC\_PLLCKSELR\_PLLSRC)\ >>\ RCC\_PLLCKSELR\_PLLSRC\_Pos)}}
\DoxyCodeLine{07952\ }
\DoxyCodeLine{07956\ }
\DoxyCodeLine{07957\ \textcolor{comment}{/*\ Include\ RCC\ HAL\ Extension\ module\ */}}
\DoxyCodeLine{07958\ \textcolor{preprocessor}{\#include\ "{}\mbox{\hyperlink{stm32h7xx__hal__rcc__ex_8h}{stm32h7xx\_hal\_rcc\_ex.h}}"{}}}
\DoxyCodeLine{07959\ }
\DoxyCodeLine{07960\ \textcolor{comment}{/*\ Exported\ functions\ -\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/*/}}
\DoxyCodeLine{07964\ }
\DoxyCodeLine{07968\ \textcolor{comment}{/*\ Initialization\ and\ de-\/initialization\ functions\ \ ******************************/}}
\DoxyCodeLine{07969\ \mbox{\hyperlink{stm32h7xx__hal__def_8h_a63c0679d1cb8b8c684fbb0632743478f}{HAL\_StatusTypeDef}}\ HAL\_RCC\_DeInit(\textcolor{keywordtype}{void});}
\DoxyCodeLine{07970\ \mbox{\hyperlink{stm32h7xx__hal__def_8h_a63c0679d1cb8b8c684fbb0632743478f}{HAL\_StatusTypeDef}}\ HAL\_RCC\_OscConfig(\mbox{\hyperlink{struct_r_c_c___osc_init_type_def}{RCC\_OscInitTypeDef}}\ *RCC\_OscInitStruct);}
\DoxyCodeLine{07971\ \mbox{\hyperlink{stm32h7xx__hal__def_8h_a63c0679d1cb8b8c684fbb0632743478f}{HAL\_StatusTypeDef}}\ HAL\_RCC\_ClockConfig(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_r_c_c___clk_init_type_def}{RCC\_ClkInitTypeDef}}\ *RCC\_ClkInitStruct,\ uint32\_t\ FLatency);}
\DoxyCodeLine{07972\ }
\DoxyCodeLine{07976\ }
\DoxyCodeLine{07980\ \textcolor{comment}{/*\ Peripheral\ Control\ functions\ \ ************************************************/}}
\DoxyCodeLine{07981\ \textcolor{keywordtype}{void}\ \ \ \ \ HAL\_RCC\_MCOConfig(uint32\_t\ RCC\_MCOx,\ uint32\_t\ RCC\_MCOSource,\ uint32\_t\ RCC\_MCODiv);}
\DoxyCodeLine{07982\ \textcolor{keywordtype}{void}\ \ \ \ \ HAL\_RCC\_EnableCSS(\textcolor{keywordtype}{void});}
\DoxyCodeLine{07983\ \textcolor{keywordtype}{void}\ \ \ \ \ HAL\_RCC\_DisableCSS(\textcolor{keywordtype}{void});}
\DoxyCodeLine{07984\ uint32\_t\ HAL\_RCC\_GetSysClockFreq(\textcolor{keywordtype}{void});}
\DoxyCodeLine{07985\ uint32\_t\ HAL\_RCC\_GetHCLKFreq(\textcolor{keywordtype}{void});}
\DoxyCodeLine{07986\ uint32\_t\ HAL\_RCC\_GetPCLK1Freq(\textcolor{keywordtype}{void});}
\DoxyCodeLine{07987\ uint32\_t\ HAL\_RCC\_GetPCLK2Freq(\textcolor{keywordtype}{void});}
\DoxyCodeLine{07988\ \textcolor{keywordtype}{void}\ \ \ \ \ HAL\_RCC\_GetOscConfig(\mbox{\hyperlink{struct_r_c_c___osc_init_type_def}{RCC\_OscInitTypeDef}}\ *RCC\_OscInitStruct);}
\DoxyCodeLine{07989\ \textcolor{keywordtype}{void}\ \ \ \ \ HAL\_RCC\_GetClockConfig(\mbox{\hyperlink{struct_r_c_c___clk_init_type_def}{RCC\_ClkInitTypeDef}}\ *RCC\_ClkInitStruct,\ uint32\_t\ *pFLatency);}
\DoxyCodeLine{07990\ \textcolor{comment}{/*\ CSS\ NMI\ IRQ\ handler\ */}}
\DoxyCodeLine{07991\ \textcolor{keywordtype}{void}\ \ \ \ \ HAL\_RCC\_NMI\_IRQHandler(\textcolor{keywordtype}{void});}
\DoxyCodeLine{07992\ \textcolor{comment}{/*\ User\ Callbacks\ in\ non\ blocking\ mode\ (IT\ mode)\ */}}
\DoxyCodeLine{07993\ \textcolor{keywordtype}{void}\ \ \ \ \ HAL\_RCC\_CSSCallback(\textcolor{keywordtype}{void});}
\DoxyCodeLine{07994\ }
\DoxyCodeLine{07998\ }
\DoxyCodeLine{08002\ }
\DoxyCodeLine{08003\ \textcolor{comment}{/*\ Private\ types\ -\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/*/}}
\DoxyCodeLine{08004\ \textcolor{comment}{/*\ Private\ variables\ -\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/*/}}
\DoxyCodeLine{08005\ \textcolor{comment}{/*\ Private\ constants\ -\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/*/}}
\DoxyCodeLine{08009\ }
\DoxyCodeLine{08010\ \textcolor{preprocessor}{\#define\ HSE\_TIMEOUT\_VALUE\ \ \ \ \ \ \ \ \ \ HSE\_STARTUP\_TIMEOUT}}
\DoxyCodeLine{08011\ \textcolor{preprocessor}{\#define\ HSI\_TIMEOUT\_VALUE\ \ \ \ \ \ \ \ \ \ (2U)\ \ \ \ }\textcolor{comment}{/*\ 2\ ms\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{08012\ \textcolor{preprocessor}{\#define\ HSI48\_TIMEOUT\_VALUE\ \ \ \ \ \ \ \ (2U)\ \ \ \ }\textcolor{comment}{/*\ 2\ ms\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{08013\ \textcolor{preprocessor}{\#define\ CSI\_TIMEOUT\_VALUE\ \ \ \ \ \ \ \ \ \ (2U)\ \ \ \ }\textcolor{comment}{/*\ 2\ ms\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{08014\ \textcolor{preprocessor}{\#define\ LSI\_TIMEOUT\_VALUE\ \ \ \ \ \ \ \ \ \ (2U)\ \ \ \ }\textcolor{comment}{/*\ 2\ ms\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{08015\ \textcolor{preprocessor}{\#define\ PLL\_TIMEOUT\_VALUE\ \ \ \ \ \ \ \ \ \ (2U)\ \ \ \ }\textcolor{comment}{/*\ 2\ ms\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{08016\ \textcolor{preprocessor}{\#define\ PLL\_FRAC\_TIMEOUT\_VALUE\ \ \ \ \ (1U)\ \ \ \ }\textcolor{comment}{/*\ PLL\ Fractional\ part\ waiting\ time\ before\ new\ latch\ enable\ :\ 1\ ms\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{08017\ \textcolor{preprocessor}{\#define\ CLOCKSWITCH\_TIMEOUT\_VALUE\ \ (5000U)\ }\textcolor{comment}{/*\ 5\ s\ \ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{08018\ \textcolor{preprocessor}{\#define\ RCC\_DBP\_TIMEOUT\_VALUE\ \ \ \ \ \ (100U)}}
\DoxyCodeLine{08019\ \textcolor{preprocessor}{\#define\ RCC\_LSE\_TIMEOUT\_VALUE\ \ \ \ \ \ LSE\_STARTUP\_TIMEOUT}}
\DoxyCodeLine{08020\ }
\DoxyCodeLine{08024\ }
\DoxyCodeLine{08025\ \textcolor{comment}{/*\ Private\ macros\ -\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/*/}}
\DoxyCodeLine{08029\ }
\DoxyCodeLine{08033\ }
\DoxyCodeLine{08034\ \textcolor{preprocessor}{\#define\ IS\_RCC\_OSCILLATORTYPE(OSCILLATOR)\ (((OSCILLATOR)\ ==\ RCC\_OSCILLATORTYPE\_NONE)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ||\ \(\backslash\)}}
\DoxyCodeLine{08035\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (((OSCILLATOR)\ \&\ RCC\_OSCILLATORTYPE\_HSE)\ ==\ RCC\_OSCILLATORTYPE\_HSE)\ ||\ \(\backslash\)}}
\DoxyCodeLine{08036\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (((OSCILLATOR)\ \&\ RCC\_OSCILLATORTYPE\_HSI)\ ==\ RCC\_OSCILLATORTYPE\_HSI)\ ||\ \(\backslash\)}}
\DoxyCodeLine{08037\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (((OSCILLATOR)\ \&\ RCC\_OSCILLATORTYPE\_CSI)\ ==\ RCC\_OSCILLATORTYPE\_CSI)\ ||\ \(\backslash\)}}
\DoxyCodeLine{08038\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (((OSCILLATOR)\ \&\ RCC\_OSCILLATORTYPE\_LSI)\ ==\ RCC\_OSCILLATORTYPE\_LSI)\ ||\ \(\backslash\)}}
\DoxyCodeLine{08039\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (((OSCILLATOR)\ \&\ RCC\_OSCILLATORTYPE\_LSE)\ ==\ RCC\_OSCILLATORTYPE\_LSE)\ ||\ \(\backslash\)}}
\DoxyCodeLine{08040\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (((OSCILLATOR)\ \&\ RCC\_OSCILLATORTYPE\_HSI48)\ ==\ RCC\_OSCILLATORTYPE\_HSI48))}}
\DoxyCodeLine{08041\ }
\DoxyCodeLine{08042\ \textcolor{preprocessor}{\#if\ defined(RCC\_CR\_HSEEXT)}}
\DoxyCodeLine{08043\ \textcolor{preprocessor}{\#define\ IS\_RCC\_HSE(HSE)\ (((HSE)\ ==\ RCC\_HSE\_OFF)\ ||\ ((HSE)\ ==\ RCC\_HSE\_ON)\ ||\ \(\backslash\)}}
\DoxyCodeLine{08044\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((HSE)\ ==\ RCC\_HSE\_BYPASS)\ ||\ ((HSE)\ ==\ RCC\_HSE\_BYPASS\_DIGITAL))}}
\DoxyCodeLine{08045\ \textcolor{preprocessor}{\#else}}
\DoxyCodeLine{08046\ \textcolor{preprocessor}{\#define\ IS\_RCC\_HSE(HSE)\ (((HSE)\ ==\ RCC\_HSE\_OFF)\ ||\ ((HSE)\ ==\ RCC\_HSE\_ON)\ ||\ \(\backslash\)}}
\DoxyCodeLine{08047\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((HSE)\ ==\ RCC\_HSE\_BYPASS))}}
\DoxyCodeLine{08048\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ RCC\_CR\_HSEEXT\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{08049\ }
\DoxyCodeLine{08050\ \textcolor{preprocessor}{\#if\ defined(RCC\_BDCR\_LSEEXT)}}
\DoxyCodeLine{08051\ \textcolor{preprocessor}{\#define\ IS\_RCC\_LSE(LSE)\ (((LSE)\ ==\ RCC\_LSE\_OFF)\ ||\ ((LSE)\ ==\ RCC\_LSE\_ON)\ ||\ \(\backslash\)}}
\DoxyCodeLine{08052\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((LSE)\ ==\ RCC\_LSE\_BYPASS)\ ||\ ((LSE)\ ==\ RCC\_LSE\_BYPASS\_DIGITAL))}}
\DoxyCodeLine{08053\ \textcolor{preprocessor}{\#else}}
\DoxyCodeLine{08054\ \textcolor{preprocessor}{\#define\ IS\_RCC\_LSE(LSE)\ (((LSE)\ ==\ RCC\_LSE\_OFF)\ ||\ ((LSE)\ ==\ RCC\_LSE\_ON)\ ||\ \(\backslash\)}}
\DoxyCodeLine{08055\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((LSE)\ ==\ RCC\_LSE\_BYPASS))}}
\DoxyCodeLine{08056\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ RCC\_BDCR\_LSEEXT\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{08057\ }
\DoxyCodeLine{08058\ \textcolor{preprocessor}{\#define\ IS\_RCC\_HSI(HSI)\ (((HSI)\ ==\ RCC\_HSI\_OFF)\ ||\ ((HSI)\ ==\ RCC\_HSI\_ON)\ \ \ \ ||\ \(\backslash\)}}
\DoxyCodeLine{08059\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((HSI)\ ==\ RCC\_HSI\_DIV1)\ ||\ ((HSI)\ ==\ RCC\_HSI\_DIV2)\ ||\ \(\backslash\)}}
\DoxyCodeLine{08060\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((HSI)\ ==\ RCC\_HSI\_DIV4)\ ||\ ((HSI)\ ==\ RCC\_HSI\_DIV8))}}
\DoxyCodeLine{08061\ }
\DoxyCodeLine{08062\ \textcolor{preprocessor}{\#define\ IS\_RCC\_HSI48(HSI48)\ (((HSI48)\ ==\ RCC\_HSI48\_OFF)\ ||\ ((HSI48)\ ==\ RCC\_HSI48\_ON))}}
\DoxyCodeLine{08063\ }
\DoxyCodeLine{08064\ \textcolor{preprocessor}{\#define\ IS\_RCC\_LSI(LSI)\ (((LSI)\ ==\ RCC\_LSI\_OFF)\ ||\ ((LSI)\ ==\ RCC\_LSI\_ON))}}
\DoxyCodeLine{08065\ }
\DoxyCodeLine{08066\ \textcolor{preprocessor}{\#define\ IS\_RCC\_CSI(CSI)\ (((CSI)\ ==\ RCC\_CSI\_OFF)\ ||\ ((CSI)\ ==\ RCC\_CSI\_ON))}}
\DoxyCodeLine{08067\ }
\DoxyCodeLine{08068\ \textcolor{preprocessor}{\#define\ IS\_RCC\_PLL(PLL)\ (((PLL)\ ==\ RCC\_PLL\_NONE)\ ||((PLL)\ ==\ RCC\_PLL\_OFF)\ ||\ \(\backslash\)}}
\DoxyCodeLine{08069\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((PLL)\ ==\ RCC\_PLL\_ON))}}
\DoxyCodeLine{08070\ }
\DoxyCodeLine{08071\ \textcolor{preprocessor}{\#define\ IS\_RCC\_PLLSOURCE(SOURCE)\ (((SOURCE)\ ==\ RCC\_PLLSOURCE\_CSI)\ \ ||\ \(\backslash\)}}
\DoxyCodeLine{08072\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((SOURCE)\ ==\ RCC\_PLLSOURCE\_HSI)\ \ ||\ \(\backslash\)}}
\DoxyCodeLine{08073\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((SOURCE)\ ==\ RCC\_PLLSOURCE\_NONE)\ ||\ \(\backslash\)}}
\DoxyCodeLine{08074\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((SOURCE)\ ==\ RCC\_PLLSOURCE\_HSE))}}
\DoxyCodeLine{08075\ }
\DoxyCodeLine{08076\ \textcolor{preprocessor}{\#define\ IS\_RCC\_PLLRGE\_VALUE(VALUE)\ (((VALUE)\ ==\ RCC\_PLL1VCIRANGE\_0)\ ||\ \(\backslash\)}}
\DoxyCodeLine{08077\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((VALUE)\ ==\ RCC\_PLL1VCIRANGE\_1)\ ||\ \(\backslash\)}}
\DoxyCodeLine{08078\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((VALUE)\ ==\ RCC\_PLL1VCIRANGE\_2)\ ||\ \(\backslash\)}}
\DoxyCodeLine{08079\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((VALUE)\ ==\ RCC\_PLL1VCIRANGE\_3))}}
\DoxyCodeLine{08080\ }
\DoxyCodeLine{08081\ \textcolor{preprocessor}{\#define\ IS\_RCC\_PLLVCO\_VALUE(VALUE)\ (((VALUE)\ ==\ RCC\_PLL1VCOWIDE)\ ||\ ((VALUE)\ ==\ RCC\_PLL1VCOMEDIUM))}}
\DoxyCodeLine{08082\ }
\DoxyCodeLine{08083\ \textcolor{preprocessor}{\#define\ IS\_RCC\_PLLFRACN\_VALUE(VALUE)\ ((VALUE)\ <=\ 8191U)}}
\DoxyCodeLine{08084\ }
\DoxyCodeLine{08085\ \textcolor{preprocessor}{\#define\ IS\_RCC\_PLLM\_VALUE(VALUE)\ ((1U\ <=\ (VALUE))\ \&\&\ ((VALUE)\ <=\ 63U))}}
\DoxyCodeLine{08086\ \textcolor{preprocessor}{\#if\ !defined(RCC\_VER\_2\_0)}}
\DoxyCodeLine{08087\ \textcolor{preprocessor}{\#define\ IS\_RCC\_PLLN\_VALUE(VALUE)\ ((4U\ <=\ (VALUE))\ \&\&\ ((VALUE)\ <=\ 512U))}}
\DoxyCodeLine{08088\ \textcolor{preprocessor}{\#else}}
\DoxyCodeLine{08089\ \textcolor{preprocessor}{\#define\ IS\_RCC\_PLLN\_VALUE(VALUE)\ ((8U\ <=\ (VALUE))\ \&\&\ ((VALUE)\ <=\ 420U))}}
\DoxyCodeLine{08090\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ !RCC\_VER\_2\_0\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{08091\ \textcolor{preprocessor}{\#define\ IS\_RCC\_PLLP\_VALUE(VALUE)\ ((1U\ <=\ (VALUE))\ \&\&\ ((VALUE)\ <=\ 128U))}}
\DoxyCodeLine{08092\ \textcolor{preprocessor}{\#define\ IS\_RCC\_PLLQ\_VALUE(VALUE)\ ((1U\ <=\ (VALUE))\ \&\&\ ((VALUE)\ <=\ 128U))}}
\DoxyCodeLine{08093\ \textcolor{preprocessor}{\#define\ IS\_RCC\_PLLR\_VALUE(VALUE)\ ((1U\ <=\ (VALUE))\ \&\&\ ((VALUE)\ <=\ 128U))}}
\DoxyCodeLine{08094\ }
\DoxyCodeLine{08095\ \textcolor{preprocessor}{\#define\ IS\_RCC\_PLLCLOCKOUT\_VALUE(VALUE)\ (((VALUE)\ ==\ RCC\_PLL1\_DIVP)\ ||\ \(\backslash\)}}
\DoxyCodeLine{08096\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((VALUE)\ ==\ RCC\_PLL1\_DIVQ)\ ||\ \(\backslash\)}}
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\DoxyCodeLine{08098\ }
\DoxyCodeLine{08099\ \textcolor{preprocessor}{\#define\ IS\_RCC\_CLOCKTYPE(CLK)\ ((1U\ <=\ (CLK))\ \&\&\ ((CLK)\ <=\ 0x3FU))}}
\DoxyCodeLine{08100\ }
\DoxyCodeLine{08101\ \textcolor{preprocessor}{\#define\ IS\_RCC\_SYSCLKSOURCE(SOURCE)\ (((SOURCE)\ ==\ RCC\_SYSCLKSOURCE\_CSI)\ ||\ \(\backslash\)}}
\DoxyCodeLine{08102\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((SOURCE)\ ==\ RCC\_SYSCLKSOURCE\_HSI)\ ||\ \(\backslash\)}}
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\DoxyCodeLine{08105\ }
\DoxyCodeLine{08106\ \textcolor{preprocessor}{\#define\ IS\_RCC\_SYSCLK(SYSCLK)\ (((SYSCLK)\ ==\ RCC\_SYSCLK\_DIV1)\ \ \ ||\ ((SYSCLK)\ ==\ RCC\_SYSCLK\_DIV2)\ \ \ ||\ \(\backslash\)}}
\DoxyCodeLine{08107\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((SYSCLK)\ ==\ RCC\_SYSCLK\_DIV4)\ \ \ ||\ ((SYSCLK)\ ==\ RCC\_SYSCLK\_DIV8)\ \ \ ||\ \(\backslash\)}}
\DoxyCodeLine{08108\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((SYSCLK)\ ==\ RCC\_SYSCLK\_DIV16)\ \ ||\ ((SYSCLK)\ ==\ RCC\_SYSCLK\_DIV64)\ \ ||\ \(\backslash\)}}
\DoxyCodeLine{08109\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((SYSCLK)\ ==\ RCC\_SYSCLK\_DIV128)\ ||\ ((SYSCLK)\ ==\ RCC\_SYSCLK\_DIV256)\ ||\ \(\backslash\)}}
\DoxyCodeLine{08110\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((SYSCLK)\ ==\ RCC\_SYSCLK\_DIV512))}}
\DoxyCodeLine{08111\ }
\DoxyCodeLine{08112\ }
\DoxyCodeLine{08113\ \textcolor{preprocessor}{\#define\ IS\_RCC\_HCLK(HCLK)\ (((HCLK)\ ==\ RCC\_HCLK\_DIV1)\ \ \ ||\ ((HCLK)\ ==\ RCC\_HCLK\_DIV2)\ \ \ ||\ \(\backslash\)}}
\DoxyCodeLine{08114\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((HCLK)\ ==\ RCC\_HCLK\_DIV4)\ \ \ ||\ ((HCLK)\ ==\ RCC\_HCLK\_DIV8)\ \ \ ||\ \(\backslash\)}}
\DoxyCodeLine{08115\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((HCLK)\ ==\ RCC\_HCLK\_DIV16)\ \ ||\ ((HCLK)\ ==\ RCC\_HCLK\_DIV64)\ \ ||\ \(\backslash\)}}
\DoxyCodeLine{08116\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((HCLK)\ ==\ RCC\_HCLK\_DIV128)\ ||\ ((HCLK)\ ==\ RCC\_HCLK\_DIV256)\ ||\ \(\backslash\)}}
\DoxyCodeLine{08117\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((HCLK)\ ==\ RCC\_HCLK\_DIV512))}}
\DoxyCodeLine{08118\ }
\DoxyCodeLine{08119\ \textcolor{preprocessor}{\#define\ IS\_RCC\_CDPCLK1(CDPCLK1)\ (((CDPCLK1)\ ==\ RCC\_APB3\_DIV1)\ ||\ ((CDPCLK1)\ ==\ RCC\_APB3\_DIV2)\ ||\ \(\backslash\)}}
\DoxyCodeLine{08120\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((CDPCLK1)\ ==\ RCC\_APB3\_DIV4)\ ||\ ((CDPCLK1)\ ==\ RCC\_APB3\_DIV8)\ ||\ \(\backslash\)}}
\DoxyCodeLine{08121\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((CDPCLK1)\ ==\ RCC\_APB3\_DIV16))}}
\DoxyCodeLine{08122\ }
\DoxyCodeLine{08123\ \textcolor{preprocessor}{\#define\ IS\_RCC\_D1PCLK1\ IS\_RCC\_CDPCLK1\ \ }\textcolor{comment}{/*\ for\ legacy\ compatibility\ between\ H7\ lines\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{08124\ }
\DoxyCodeLine{08125\ \textcolor{preprocessor}{\#define\ IS\_RCC\_PCLK1(PCLK1)\ (((PCLK1)\ ==\ RCC\_APB1\_DIV1)\ ||\ ((PCLK1)\ ==\ RCC\_APB1\_DIV2)\ ||\ \(\backslash\)}}
\DoxyCodeLine{08126\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((PCLK1)\ ==\ RCC\_APB1\_DIV4)\ ||\ ((PCLK1)\ ==\ RCC\_APB1\_DIV8)\ ||\ \(\backslash\)}}
\DoxyCodeLine{08127\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((PCLK1)\ ==\ RCC\_APB1\_DIV16))}}
\DoxyCodeLine{08128\ }
\DoxyCodeLine{08129\ \textcolor{preprocessor}{\#define\ IS\_RCC\_PCLK2(PCLK2)\ (((PCLK2)\ ==\ RCC\_APB2\_DIV1)\ ||\ ((PCLK2)\ ==\ RCC\_APB2\_DIV2)\ ||\ \(\backslash\)}}
\DoxyCodeLine{08130\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((PCLK2)\ ==\ RCC\_APB2\_DIV4)\ ||\ ((PCLK2)\ ==\ RCC\_APB2\_DIV8)\ ||\ \(\backslash\)}}
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\DoxyCodeLine{08133\ \textcolor{preprocessor}{\#define\ IS\_RCC\_SRDPCLK1(SRDPCLK1)\ (((SRDPCLK1)\ ==\ RCC\_APB4\_DIV1)\ ||\ ((SRDPCLK1)\ ==\ RCC\_APB4\_DIV2)\ ||\ \(\backslash\)}}
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\DoxyCodeLine{08139\ \textcolor{preprocessor}{\#define\ IS\_RCC\_RTCCLKSOURCE(SOURCE)\ (((SOURCE)\ ==\ RCC\_RTCCLKSOURCE\_LSE)\ \ \ \ \ \ \ ||\ ((SOURCE)\ ==\ RCC\_RTCCLKSOURCE\_LSI)\ \ \ \ \ \ \ ||\ \(\backslash\)}}
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\DoxyCodeLine{08172\ \textcolor{preprocessor}{\#define\ IS\_RCC\_MCO(MCOx)\ (((MCOx)\ ==\ RCC\_MCO1)\ ||\ ((MCOx)\ ==\ RCC\_MCO2))}}
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\DoxyCodeLine{08178\ \textcolor{preprocessor}{\#define\ IS\_RCC\_MCO2SOURCE(SOURCE)\ (((SOURCE)\ ==\ RCC\_MCO2SOURCE\_SYSCLK)\ \ \ \ ||\ ((SOURCE)\ ==\ RCC\_MCO2SOURCE\_PLL2PCLK)\ ||\ \(\backslash\)}}
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\DoxyCodeLine{08182\ \textcolor{preprocessor}{\#define\ IS\_RCC\_MCODIV(DIV)\ (((DIV)\ ==\ RCC\_MCODIV\_1)\ \ ||\ ((DIV)\ ==\ RCC\_MCODIV\_2)\ \ \ ||\ \(\backslash\)}}
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\DoxyCodeLine{08234\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ RCC\_CR\_D2CKRDY\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{08235\ }
\DoxyCodeLine{08236\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*DUAL\_CORE*/}\textcolor{preprocessor}{}}
\DoxyCodeLine{08237\ }
\DoxyCodeLine{08238\ \textcolor{preprocessor}{\#define\ IS\_RCC\_HSICALIBRATION\_VALUE(VALUE)\ ((VALUE)\ <=\ 0x7FU)}}
\DoxyCodeLine{08239\ \textcolor{preprocessor}{\#define\ IS\_RCC\_CSICALIBRATION\_VALUE(VALUE)\ ((VALUE)\ <=\ 0x3FU)}}
\DoxyCodeLine{08240\ }
\DoxyCodeLine{08241\ \textcolor{preprocessor}{\#define\ IS\_RCC\_STOP\_WAKEUPCLOCK(SOURCE)\ (((SOURCE)\ ==\ RCC\_STOP\_WAKEUPCLOCK\_CSI)\ ||\ \(\backslash\)}}
\DoxyCodeLine{08242\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((SOURCE)\ ==\ RCC\_STOP\_WAKEUPCLOCK\_HSI))}}
\DoxyCodeLine{08243\ }
\DoxyCodeLine{08244\ \textcolor{preprocessor}{\#define\ IS\_RCC\_STOP\_KERWAKEUPCLOCK(SOURCE)\ (((SOURCE)\ ==\ RCC\_STOP\_KERWAKEUPCLOCK\_CSI)\ ||\ \(\backslash\)}}
\DoxyCodeLine{08245\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((SOURCE)\ ==\ RCC\_STOP\_KERWAKEUPCLOCK\_HSI))}\textcolor{preprocessor}{}}
\DoxyCodeLine{08249\ }
\DoxyCodeLine{08253\ }
\DoxyCodeLine{08257\ }
\DoxyCodeLine{08261\ \textcolor{preprocessor}{\#ifdef\ \_\_cplusplus}}
\DoxyCodeLine{08262\ \}}
\DoxyCodeLine{08263\ \textcolor{preprocessor}{\#endif}}
\DoxyCodeLine{08264\ }
\DoxyCodeLine{08265\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ STM32H7xx\_HAL\_RCC\_H\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{08266\ }

\end{DoxyCode}
